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Merge branch 'feature/load_elf' into 'master'

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Support ELF files loadable with gdb

Closes IDF-335

See merge request espressif/esp-idf!5779
This commit is contained in:
Ivan Grokhotkov
2019-09-27 19:36:25 +08:00
parent 9c4b4aec62 5a916ce126
commit c496268b10
24 changed files with 387 additions and 55 deletions
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5
components/esp32/Kconfig
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@@ -738,6 +738,11 @@ menu "ESP32-specific"
Enabling this setting adds approximately 1KB to the app's IRAM usage.
config ESP32_APP_INIT_CLK
bool
default y if ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
default y if APP_BUILD_TYPE_ELF_RAM
config ESP32_RTCDATA_IN_FAST_MEM
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
default n

4
components/esp32/clk.c
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@@ -75,7 +75,7 @@ void esp_clk_init(void)
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
rtc_init(cfg);
#ifdef CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
#if (CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_ESP32_APP_INIT_CLK)
/* Check the bootloader set the XTAL frequency.
Bootloaders pre-v2.1 don't do this.
@@ -293,6 +293,8 @@ void esp_perip_clk_init(void)
DPORT_I2S1_CLK_EN |
DPORT_SPI_DMA_CLK_EN;
common_perip_clk &= ~DPORT_SPI01_CLK_EN;
#if CONFIG_SPIRAM_SPEED_80M
//80MHz SPIRAM uses SPI2/SPI3 as well; it's initialized before this is called. Because it is used in
//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'

45
components/esp32/cpu_start.c
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@@ -72,6 +72,11 @@
#include "esp_efuse.h"
#include "bootloader_flash_config.h"
#ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
#include "esp32/rom/efuse.h"
#include "esp32/rom/spi_flash.h"
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
#define STRINGIFY(s) STRINGIFY2(s)
#define STRINGIFY2(s) #s
@@ -391,6 +396,32 @@ void start_cpu0_default(void)
#ifndef CONFIG_FREERTOS_UNICORE
esp_dport_access_int_init();
#endif
bootloader_flash_update_id();
#if !CONFIG_SPIRAM_BOOT_INIT
// Read the application binary image header. This will also decrypt the header if the image is encrypted.
esp_image_header_t fhdr = {0};
#ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_40M;
fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
extern void esp_rom_spiflash_attach(uint32_t, bool);
esp_rom_spiflash_attach(ets_efuse_get_spiconfig(), false);
esp_rom_spiflash_unlock();
#else
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
// the binary header through cache by accessing SOC_DROM_LOW address.
memcpy(&fhdr, (void*) SOC_DROM_LOW, sizeof(fhdr));
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
// If psram is uninitialized, we need to improve some flash configuration.
bootloader_flash_clock_config(&fhdr);
bootloader_flash_gpio_config(&fhdr);
bootloader_flash_dummy_config(&fhdr);
bootloader_flash_cs_timing_config();
#endif //!CONFIG_SPIRAM_BOOT_INIT
spi_flash_init();
/* init default OS-aware flash access critical section */
spi_flash_guard_set(&g_flash_guard_default_ops);
@@ -424,20 +455,6 @@ void start_cpu0_default(void)
esp_coex_adapter_register(&g_coex_adapter_funcs);
#endif
bootloader_flash_update_id();
#if !CONFIG_SPIRAM_BOOT_INIT
// Read the application binary image header. This will also decrypt the header if the image is encrypted.
esp_image_header_t fhdr = {0};
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
// the binary header through cache by accessing SOC_DROM_LOW address.
memcpy(&fhdr, (void*) SOC_DROM_LOW, sizeof(fhdr));
// If psram is uninitialized, we need to improve some flash configuration.
bootloader_flash_clock_config(&fhdr);
bootloader_flash_gpio_config(&fhdr);
bootloader_flash_dummy_config(&fhdr);
bootloader_flash_cs_timing_config();
#endif
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
ESP_TASK_MAIN_STACK, NULL,
ESP_TASK_MAIN_PRIO, NULL, 0);

16
components/esp32/ld/esp32.ld
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@@ -49,6 +49,7 @@ MEMORY
/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Even though the segment name is iram, it is actually mapped to flash
*/
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
@@ -58,6 +59,7 @@ MEMORY
which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
*/
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
@@ -72,10 +74,12 @@ MEMORY
dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* RTC fast memory (executable). Persists over deep sleep.
*/
@@ -116,3 +120,15 @@ REGION_ALIAS("rtc_data_location", rtc_slow_seg );
#else
REGION_ALIAS("rtc_data_location", rtc_data_seg );
#endif
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", iram0_2_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

28
components/esp32/ld/esp32.project.ld.in
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@@ -161,12 +161,8 @@ SECTIONS
mapping[iram0_text]
_iram_text_end = ABSOLUTE(.);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
.dram0.data :
{
_data_start = ABSOLUTE(.);
@@ -312,7 +308,7 @@ SECTIONS
*(.tbss.*)
_thread_local_end = ABSOLUTE(.);
. = ALIGN(4);
} >drom0_0_seg
} >default_rodata_seg
.flash.text :
{
@@ -334,5 +330,25 @@ SECTIONS
the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} >iram0_2_seg
} >default_code_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
. = ALIGN (4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
. = ALIGN (8);
_heap_start = ABSOLUTE(.);
} > dram0_0_seg
}
ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")

8
components/esp32/ld/esp32_fragments.lf
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@@ -50,8 +50,12 @@ entries:
[scheme:default]
entries:
text -> flash_text
rodata -> flash_rodata
if APP_BUILD_USE_FLASH_SECTIONS = y:
text -> flash_text
rodata -> flash_rodata
else:
text -> iram0_text
rodata -> dram0_data
data -> dram0_data
bss -> dram0_bss
common -> dram0_bss

2
components/esp32/panic.c
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@@ -450,7 +450,7 @@ static void esp_panic_dig_reset(void)
;
}
}
#endif
#endif // CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT
static void putEntry(uint32_t pc, uint32_t sp)
{