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Merge branch 'fix/esp32s3_ununsed_dcache_as_dram_v5.1' into 'release/v5.1'

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esp_hw_support: Update the memory ptr location/property checks to include the unused DCACHE added to DRAM (v5.1)

See merge request espressif/esp-idf!23303
This commit is contained in:
Mahavir Jain
2023-04-27 22:09:55 +08:00
parent 1a03cb02c2 16f3317496
commit c49dce48eb
3 changed files with 32 additions and 2 deletions
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2
components/soc/esp32s3/include/soc/soc.h
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@@ -218,7 +218,7 @@
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3FC88000
#define SOC_MEM_INTERNAL_HIGH 0x403E2000
#define SOC_MEM_INTERNAL_HIGH 0x403E0000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fceb710