alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-10 04:43:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

newlib: implement time syscalls

Browse Source
This commit is contained in:
Ivan Grokhotkov
2016-11-02 17:17:28 +08:00
parent 3af7872839
commit c534dedf2d
8 changed files with 211 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
components/esp32/Kconfig
View File

@@ -319,6 +319,35 @@ config BROWNOUT_DET_RESETDELAY
before trying to restart the chip. You can set the delay here.
choice ESP32_TIME_SYSCALL
prompt "Timers used for gettimeofday function"
default ESP32_TIME_SYSCALL_USE_RTC_FRC1
help
This setting defines which hardware timers are used to
implement 'gettimeofday' function in C library.
- If only FRC1 timer is used, gettimeofday will provide time at
microsecond resolution. Time will not be preserved when going
into deep sleep mode.
- If both FRC1 and RTC timers are used, timekeeping will
continue in deep sleep. Time will be reported at 1 microsecond
resolution.
- If only RTC timer is used, timekeeping will continue in
deep sleep, but time will be measured at 6.(6) microsecond
resolution. Also the gettimeofday function itself may take
longer to run.
- If no timers are used, gettimeofday function return -1 and
set errno to ENOSYS.
config ESP32_TIME_SYSCALL_USE_RTC
bool "RTC"
config ESP32_TIME_SYSCALL_USE_RTC_FRC1
bool "RTC and FRC1"
config ESP32_TIME_SYSCALL_USE_FRC1
bool "FRC1"
config ESP32_TIME_SYSCALL_USE_NONE
bool "None"
endchoice
endmenu

3
components/esp32/cpu_start.c
View File

@@ -169,7 +169,8 @@ void start_cpu0_default(void)
#if CONFIG_TASK_WDT
esp_task_wdt_init();
#endif
esp_setup_syscalls();
esp_setup_syscall_table();
esp_setup_time_syscalls();
esp_vfs_dev_uart_register();
esp_reent_init(_GLOBAL_REENT);
const char* default_uart_dev = "/dev/uart/0";

49
components/esp32/include/soc/frc_timer_reg.h Normal file
View File

@@ -0,0 +1,49 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_FRC_TIMER_REG_H_
#define _SOC_FRC_TIMER_REG_H_
#include "soc.h"
/**
* These are the register definitions for "legacy" timers
*/
#define REG_FRC_TIMER_BASE(i) (DR_REG_FRC_TIMER_BASE + i*0x20)
#define FRC_TIMER_LOAD_REG(i) (REG_FRC_TIMER_BASE(i) + 0x0) // timer load value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_LOAD_VALUE(i) ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_LOAD_VALUE_S 0
#define FRC_TIMER_COUNT_REG(i) (REG_FRC_TIMER_BASE(i) + 0x4) // timer count value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_COUNT ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_COUNT_S 0
#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
#define FRC_TIMER_INT_ENABLE (BIT(8)) // enable interrupt
#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload
#define FRC_TIMER_PRESCALER 0x00000007 // 0: divide by 1, 2: divide by 16, 4: divide by 256
#define FRC_TIMER_PRESCALER_S 1
#define FRC_TIMER_EDGE_INT (BIT(0)) // 0: level, 1: edge
#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC)
#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt
#define FRC_TIMER_ALARM_REG(i) (REG_FRC_TIMER_BASE(i) + 0x10) // timer alarm value; register only present for i == 1
#define FRC_TIMER_ALARM 0xFFFFFFFF
#define FRC_TIMER_ALARM_S 0
#endif //_SOC_FRC_TIMER_REG_H_

3
components/esp32/include/soc/rtc_cntl_reg.h
View File

@@ -239,6 +239,9 @@
#define RTC_CNTL_TIME_VALID_V 0x1
#define RTC_CNTL_TIME_VALID_S 30
/* frequency of RTC slow clock, Hz */
#define RTC_CTNL_SLOWCLK_FREQ 150000
#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10)
/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: RTC timer low 32 bits*/

9
components/esp32/include/soc/soc.h
View File

@@ -148,6 +148,7 @@
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SARADC_BASE 0x3ff48800
@@ -281,9 +282,9 @@
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 22 3 extern edge FRC1 timer
* 23 3 extern level
* 24 4 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level Reserved Reserved
* 26 5 extern level Reserved Reserved
* 27 3 extern level Reserved Reserved
@@ -301,8 +302,10 @@
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
//CPU0 Intrrupt number used in ROM, should be cancelled in SDK
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5