refactor(uart): add support to be able to test LP_UART port

Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value
could cause the FIFO become empty before filling next data into the FIFO
when the buadrate is high. TX_DONE interrupt would raise before actual
transmission complete in such case.

components/driver/test_apps/uart/pytest_uart.py

@@ -1,8 +1,17 @@
-# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 
+input_argv = {
+    'esp32': ['uart'],
+    'esp32s2': ['uart'],
+    'esp32s3': ['uart'],
+    'esp32c3': ['uart'],
+    'esp32c2': ['uart'],
+    'esp32c6': ['uart', 'lp_uart'],
+    'esp32h2': ['uart'],
+}
+
 
 @pytest.mark.supported_targets
 @pytest.mark.generic
@@ -15,4 +24,14 @@ import pytest
     indirect=True,
 )
 def test_uart_single_dev(case_tester) -> None:                # type: ignore
-    case_tester.run_all_normal_cases(reset=True)
+    dut = case_tester.dut
+    chip_type = dut.app.target
+    for uart_port in input_argv.get(chip_type, []):
+        for case in case_tester.test_menu:
+            dut.serial.hard_reset()
+            dut._get_ready()
+            dut.confirm_write(case.index, expect_str=f'Running {case.name}...')
+
+            dut.expect("select to test 'uart' or 'lp_uart' port", timeout=10)
+            dut.write(f'{uart_port}')
+            dut.expect_unity_test_output()