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Merge branch 'ci/backport_i2s_ci_fix_to_v5.3' into 'release/v5.3'

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ci(i2s&parlio): backport i2s and parlio ci fix (v5.3)

See merge request espressif/esp-idf!34587
This commit is contained in:
Jiang Jiang Jian
2024-11-14 19:00:39 +08:00
parent 62933660a8 035f2f8280
commit c5a3c7e78f
7 changed files with 47 additions and 19 deletions
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12
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -1107,10 +1107,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
int
default 16
config SOC_PARLIO_TX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SIZE_BY_DMA
bool
default y

3
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -420,7 +420,10 @@
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
/*--------------------------- MPI CAPS ---------------------------------------*/