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Merge branch 'esp32p4/add_aes_gcm_support' into 'master'

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feat: add AES-GCM support for ESP32-P4

See merge request espressif/esp-idf!29516
This commit is contained in:
Mahavir Jain
2024-03-27 11:40:26 +08:00
parent f85ddd17ce c4f052cee4
commit c658351eab
9 changed files with 488 additions and 69 deletions
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4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -247,6 +247,10 @@ config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_SUPPORT_GCM
bool
default y
config SOC_AES_GDMA
bool
default y

51
components/soc/esp32p4/include/soc/aes_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -216,6 +216,19 @@ extern "C" {
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_ENDIAN_REG register
* AES Endian configure register
*/
#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
#define AES_ENDIAN 0x0000003FU
#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
#define AES_ENDIAN_V 0x0000003FU
#define AES_ENDIAN_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
@@ -314,6 +327,42 @@ extern "C" {
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_AAD_BLOCK_NUM_REG register
* Additional Authential Data block number register
*/
#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_S 0
/** AES_REMAINDER_BIT_NUM_REG register
* AES remainder bit number register
*/
#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
#define AES_REMAINDER_BIT_NUM 0x0000007FU
#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
#define AES_REMAINDER_BIT_NUM_V 0x0000007FU
#define AES_REMAINDER_BIT_NUM_S 0
/** AES_CONTINUE_REG register
* AES continue register
*/
#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
#define AES_CONTINUE (BIT(0))
#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
#define AES_CONTINUE_V 0x00000001U
#define AES_CONTINUE_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/

64
components/soc/esp32p4/include/soc/aes_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -240,6 +240,21 @@ typedef union {
uint32_t val;
} aes_mode_reg_t;
/** Type of endian register
* AES Endian configure register
*/
typedef union {
struct {
/** endian : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
uint32_t endian:6;
uint32_t reserved_6:26;
};
uint32_t val;
} aes_endian_reg_t;
/** Type of block_mode register
* AES cipher block mode register
*/
@@ -282,6 +297,33 @@ typedef union {
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of aad_block_num register
* Additional Authential Data block number register
*/
typedef union {
struct {
/** aad_block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
uint32_t aad_block_num:32;
};
uint32_t val;
} aes_aad_block_num_reg_t;
/** Type of remainder_bit_num register
* AES remainder bit number register
*/
typedef union {
struct {
/** remainder_bit_num : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
uint32_t remainder_bit_num:7;
uint32_t reserved_7:25;
};
uint32_t val;
} aes_remainder_bit_num_reg_t;
/** Group: Control/Status register */
/** Type of trigger register
@@ -327,6 +369,20 @@ typedef union {
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of continue register
* AES continue register
*/
typedef union {
struct {
/** continue : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_continue_reg_t;
/** Type of dma_exit register
* AES-DMA exit config
*/
@@ -409,7 +465,7 @@ typedef struct {
volatile aes_text_out_2_reg_t text_out_2;
volatile aes_text_out_3_reg_t text_out_3;
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_endian_reg_t endian;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
@@ -420,7 +476,9 @@ typedef struct {
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_aad_block_num_reg_t aad_block_num;
volatile aes_remainder_bit_num_reg_t remainder_bit_num;
volatile aes_continue_reg_t conti;
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;

1
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -96,6 +96,7 @@
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
#define SOC_AES_SUPPORT_GCM (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_AES_GDMA (1)