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Merge branch 'feature/uart_sleep_retention_support_c5_c61_v5.4' into 'release/v5.4'

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feat(uart): support uart sleep retention on C5/C61 (v5.4)

See merge request espressif/esp-idf!35400
This commit is contained in:
morris
2025-01-07 10:29:23 +08:00
parent 51bae98066 cfcedfe42d
commit c670044eab
20 changed files with 198 additions and 95 deletions
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21
components/soc/esp32c5/register/soc/lp_uart_reg.h
View File

@@ -1287,6 +1287,27 @@ extern "C" {
* LP UART core clock configuration
*/
#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_B 0x0000003FU
#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
#define LP_UART_SCLK_DIV_B_V 0x0000003FU
#define LP_UART_SCLK_DIV_B_S 0
/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_A 0x0000003FU
#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
#define LP_UART_SCLK_DIV_A_V 0x0000003FU
#define LP_UART_SCLK_DIV_A_S 6
/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_NUM 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_S 12
/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable LP UART TX clock.\\
* 0: Disable\\

10
components/soc/esp32c5/register/soc/uart_struct.h
View File

@@ -16,7 +16,7 @@ extern "C" {
*/
typedef union {
struct {
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
/** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
* Represents the data UART $n read from FIFO.\\
* Measurement unit: byte.
*/
@@ -950,17 +950,17 @@ typedef union {
* The denominator of the frequency divider factor.'
* Only available to LP UART instance
*/
uint32_t sclk_div_b:6;
uint32_t sclk_div_b:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_a:6;
uint32_t sclk_div_a:6; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_num:8;
uint32_t sclk_div_num:8; /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
uint32_t reserved_20:4;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable UART TX clock.\\
@@ -1308,7 +1308,7 @@ typedef union {
} uart_id_reg_t;
typedef struct {
typedef struct uart_dev_s {
volatile uart_fifo_reg_t fifo;
volatile uart_int_raw_reg_t int_raw;
volatile uart_int_st_reg_t int_st;