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Merge branch 'feature/uart_sleep_retention_support_c5_c61_v5.4' into 'release/v5.4'

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feat(uart): support uart sleep retention on C5/C61 (v5.4)

See merge request espressif/esp-idf!35400
This commit is contained in:
morris
2025-01-07 10:29:23 +08:00
parent 51bae98066 cfcedfe42d
commit c670044eab
20 changed files with 198 additions and 95 deletions
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10
components/soc/esp32c61/include/soc/retention_periph_defs.h
View File

@@ -34,10 +34,11 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_I2C0 = 12,
SLEEP_RETENTION_MODULE_UART0 = 14,
SLEEP_RETENTION_MODULE_UART1 = 15,
SLEEP_RETENTION_MODULE_ETM0 = 16,
SLEEP_RETENTION_MODULE_GPSPI2 = 17,
SLEEP_RETENTION_MODULE_LEDC = 18,
SLEEP_RETENTION_MODULE_I2S0 = 19,
SLEEP_RETENTION_MODULE_UART2 = 16,
SLEEP_RETENTION_MODULE_ETM0 = 17,
SLEEP_RETENTION_MODULE_GPSPI2 = 18,
SLEEP_RETENTION_MODULE_LEDC = 19,
SLEEP_RETENTION_MODULE_I2S0 = 20,
/* Modem module, which includes WiFi, BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_WIFI_MAC = 26,
@@ -62,6 +63,7 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \

3
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -404,7 +404,8 @@
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1)
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)

12
components/soc/esp32c61/uart_periph.c
View File

@@ -120,11 +120,11 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
* UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
* UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
* UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG
*/
#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
#define UART_RETENTION_ADDR_MAP_REGS_CNT 22
#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
static const uint32_t uart_regs_map[4] = {0x807fff6d, 0x10, 0x0, 0x0};
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
@@ -147,6 +147,7 @@ static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
static const regdma_entries_config_t uart2_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(2);
const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
[0] = {
@@ -159,4 +160,9 @@ const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
.regdma_entry_array = uart1_regdma_entries,
.array_size = ARRAY_SIZE(uart1_regdma_entries),
},
[2] = {
.module = SLEEP_RETENTION_MODULE_UART2,
.regdma_entry_array = uart2_regdma_entries,
.array_size = ARRAY_SIZE(uart2_regdma_entries),
},
};