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Merge branch 'feature/uart_sleep_retention_support_c5_c61_v5.4' into 'release/v5.4'

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feat(uart): support uart sleep retention on C5/C61 (v5.4)

See merge request espressif/esp-idf!35400
This commit is contained in:
morris
2025-01-07 10:29:23 +08:00
parent 51bae98066 cfcedfe42d
commit c670044eab
20 changed files with 198 additions and 95 deletions
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23
components/soc/esp32p4/register/soc/lp_uart_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1235,6 +1235,27 @@ extern "C" {
* UART core clock configuration
*/
#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_B 0x0000003FU
#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
#define LP_UART_SCLK_DIV_B_V 0x0000003FU
#define LP_UART_SCLK_DIV_B_S 0
/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_A 0x0000003FU
#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
#define LP_UART_SCLK_DIV_A_V 0x0000003FU
#define LP_UART_SCLK_DIV_A_S 6
/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_NUM 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_S 12
/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/

2
components/soc/esp32p4/register/soc/uart_struct.h
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@@ -1263,7 +1263,7 @@ typedef struct uart_dev_t{
volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */
volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */
volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */
volatile uart_clk_conf_reg_t clk_conf; /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
volatile uart_clk_conf_reg_t clk_conf;
volatile uart_date_reg_t date;
volatile uart_afifo_status_reg_t afifo_status;
uint32_t reserved_094;

6
components/soc/esp32p4/uart_periph.c
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@@ -220,11 +220,11 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
* UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
* UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
* UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG
*/
#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
#define UART_RETENTION_ADDR_MAP_REGS_CNT 22
#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
static const uint32_t uart_regs_map[4] = {0x807fff6d, 0x10, 0x0, 0x0};
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \