refactor(hal/usb): Remove usb_fsls_phy_ll.h

For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.

This commit does the following:

- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.

components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h

@@ -1,34 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/usb_serial_jtag_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configures the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
-{
-    // USB_Serial_JTAG use internal PHY
-    hw->conf0.phy_sel = 0;
-    // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
-    hw->conf0.pad_pull_override = 0;
-    // Enable USB D+ pullup
-    hw->conf0.dp_pullup = 1;
-    // Enable USB pad function
-    hw->conf0.usb_pad_enable = 1;
-}
-
-#ifdef __cplusplus
-}
-#endif