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bootloader: fix analog reset on C6 and H2

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This commit is contained in:
Michael (XIAO Xufeng)
2023-03-06 11:46:19 +08:00
committed by Xiao Xufeng
parent 1a1b0036a6
commit c7b852b7c7
10 changed files with 37 additions and 80 deletions
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2
components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
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@@ -2727,7 +2727,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C)

2
components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
View File

@@ -3475,7 +3475,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
/** RTC_CNTL_GPIO_WAKEUP_REG register