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clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem
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69
components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
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69
components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/regi2c_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Reset (Disable) the I2C internal bus for all regi2c registers
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*/
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static inline void regi2c_ctrl_ll_i2c_reset(void)
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{
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// On ESP32-H2, don't need to do anything (indeed do need? not fully supported yet?)
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// SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
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}
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/**
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* @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
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*/
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static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
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{
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// On ESP32-H2, don't need to do anything (indeed do need? not fully supported yet?)
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// CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
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}
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/**
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* @brief Start BBPLL self-calibration
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
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{
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REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
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REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
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}
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/**
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* @brief Stop BBPLL self-calibration
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*
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* This helps to prevent BBPLL jitter (phenomenon is significant on ESP32H2)
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
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{
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REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
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REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
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}
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/**
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* @brief Check whether BBPLL calibration is done
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*
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* @return True if calibration is done; otherwise false
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*/
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static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
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{
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return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
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}
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#ifdef __cplusplus
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}
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#endif
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