feat(esp32c5mp): support to run hello world on esp32c5 mp

components/esp_system/ld/esp32c5/mp/memory.ld.in

@@ -15,20 +15,9 @@
 #include "sdkconfig.h"
 #include "ld.common"
 
-/**
- * physical memory is mapped twice to the vritual address (IRAM and DRAM).
- * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
- */
-#define SRAM_IRAM_START     0x40800000
-#define SRAM_DRAM_START     0x40800000
-
-#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
-#define SRAM_DRAM_END       0x4086E610 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
-
-#define SRAM_IRAM_ORG       (SRAM_IRAM_START)
-#define SRAM_DRAM_ORG       (SRAM_DRAM_START)
-
-#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
+#define SRAM_SEG_START     0x40800000
+#define SRAM_SEG_END       0x4086E610  /* 2nd stage bootloader iram_loader_seg start address */
+#define SRAM_SEG_SIZE      SRAM_SEG_END - SRAM_SEG_START
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 /*
@@ -37,8 +26,6 @@
 #define IDRAM0_2_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 8)
 #endif
 
-#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
-
 MEMORY
 {
   /**
@@ -47,9 +34,6 @@ MEMORY
    *  are connected to the data port of the CPU and eg allow byte-wise access.
    */
 
-  /* IRAM for PRO CPU. */
-  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
-
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped instruction data */
   irom_seg (RX) :                    org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
@@ -67,7 +51,7 @@ MEMORY
    * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
    * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
    */
-  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
+  sram_seg (RWX) :                   org = SRAM_SEG_START, len = SRAM_SEG_SIZE
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
@@ -96,7 +80,7 @@ MEMORY
   lp_reserved_seg(RW) :        org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
 }
 
-/* Heap ends at top of dram0_0_seg */
+/* Heap ends at top of sram_seg */
 _heap_end = 0x40000000;
 
 _data_seg_org = ORIGIN(rtc_data_seg);
@@ -115,13 +99,13 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   REGION_ALIAS("default_code_seg", irom_seg);
 #else
-  REGION_ALIAS("default_code_seg", iram0_0_seg);
+  REGION_ALIAS("default_code_seg", sram_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   REGION_ALIAS("default_rodata_seg", drom_seg);
 #else
-  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+  REGION_ALIAS("default_rodata_seg", sram_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 /**

components/esp_system/ld/esp32c5/mp/sections.ld.in

@@ -161,13 +161,13 @@ SECTIONS
 
     mapping[iram0_text]
 
-  } > iram0_0_seg
+  } > sram_seg
 
   /* Marks the end of IRAM code segment */
   .iram0.text_end (NOLOAD) :
   {
     ALIGNED_SYMBOL(4, _iram_text_end)
-  } > iram0_0_seg
+  } > sram_seg
 
   .iram0.data :
   {
@@ -176,7 +176,7 @@ SECTIONS
     mapping[iram0_data]
 
     _iram_data_end = ABSOLUTE(.);
-  } > iram0_0_seg
+  } > sram_seg
 
   .iram0.bss (NOLOAD) :
   {
@@ -186,16 +186,16 @@ SECTIONS
 
     _iram_bss_end = ABSOLUTE(.);
     ALIGNED_SYMBOL(16, _iram_end)
-  } > iram0_0_seg
+  } > sram_seg
 
   /**
-   * This section is required to skip .iram0.text area because iram0_0_seg and
-   * dram0_0_seg reflect the same address space on different buses.
+   * This section is required to skip .iram0.text area because sram_seg and
+   * sram_seg reflect the same address space on different buses.
    */
   .dram0.dummy (NOLOAD):
   {
-    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
-  } > dram0_0_seg
+    . = ORIGIN(sram_seg) + _iram_end - _iram_start;
+  } > sram_seg
 
   .dram0.data :
   {
@@ -212,7 +212,7 @@ SECTIONS
     mapping[dram0_data]
 
     _data_end = ABSOLUTE(.);
-  } > dram0_0_seg
+  } > sram_seg
 
   /**
    * This section holds data that should not be initialized at power up.
@@ -227,7 +227,7 @@ SECTIONS
     *(.noinit .noinit.*)
 
     ALIGNED_SYMBOL(4, _noinit_end)
-  } > dram0_0_seg
+  } > sram_seg
 
   /* Shared RAM */
   .dram0.bss (NOLOAD) :
@@ -241,9 +241,9 @@ SECTIONS
     mapping[dram0_bss]
 
     ALIGNED_SYMBOL(8, _bss_end)
-  } > dram0_0_seg
+  } > sram_seg
 
-  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
+  ASSERT(((_bss_end - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "DRAM segment data does not fit.")
 
   .flash.text :
   {
@@ -440,7 +440,7 @@ SECTIONS
   .dram0.heap_start (NOLOAD) :
   {
     ALIGNED_SYMBOL(16, _heap_start)
-  } > dram0_0_seg
+  } > sram_seg
 
   /**
    * Discarding .rela.* sections results in the following mapping:
@@ -451,8 +451,8 @@ SECTIONS
   /DISCARD/ : { *(.rela.*) }
 }
 
-ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
+ASSERT(((_iram_end - ORIGIN(sram_seg)) <= LENGTH(sram_seg)),
           "IRAM0 segment data does not fit.")
 
-ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
+ASSERT(((_heap_start - ORIGIN(sram_seg)) <= LENGTH(sram_seg)),
           "DRAM segment data does not fit.")