Merge branch 'feature/io_mux_use_pll80_c6' into 'master'

io_mux: support change clock source to PLL_F80M

Closes IDF-6342 and IDF-6345

See merge request espressif/esp-idf!21613

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -307,6 +307,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
     bool
     default y
 
+config SOC_GPIO_FILTER_CLK_SUPPORT_APB
+    bool
+    default y
+
 config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
     bool
     default y
@@ -555,6 +559,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
     int
     default 4
 
+config SOC_SDM_CLK_SUPPORT_APB
+    bool
+    default y
+
 config SOC_SPI_PERIPH_NUM
     int
     default 2

components/soc/esp32c3/include/soc/clk_tree_defs.h

@@ -243,7 +243,7 @@ typedef enum {
     I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
 } soc_periph_i2c_clk_src_t;
 
-//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
 
 /**
  * @brief Array initializer for all supported clock sources of SDM
@@ -258,6 +258,22 @@ typedef enum {
     SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
 } soc_periph_sdm_clk_src_t;
 
+//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Glitch Filter
+ */
+#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
+
+/**
+ * @brief Glitch filter clock source
+ */
+
+typedef enum {
+    GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB,      /*!< Select APB clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,  /*!< Select APB clock as the default clock choice */
+} soc_periph_glitch_filter_clk_src_t;
+
 //////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32c3/include/soc/soc_caps.h

@@ -145,6 +145,7 @@
 #define SOC_GPIO_PORT                      1U
 #define SOC_GPIO_PIN_COUNT                 22
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
+#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
 
 // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
 // On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
@@ -263,6 +264,7 @@
 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/
 #define SOC_SDM_GROUPS             1U
 #define SOC_SDM_CHANNELS_PER_GROUP 4
+#define SOC_SDM_CLK_SUPPORT_APB    1
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM          2