Merge branch 'feature/io_mux_use_pll80_c6' into 'master'

io_mux: support change clock source to PLL_F80M

Closes IDF-6342 and IDF-6345

See merge request espressif/esp-idf!21613

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -311,6 +311,14 @@ config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
     int
     default 8
 
+config SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_ETM
     bool
     default y
@@ -663,6 +671,14 @@ config SOC_SDM_CHANNELS_PER_GROUP
     int
     default 4
 
+config SOC_SDM_CLK_SUPPORT_PLL_F80M
+    bool
+    default y
+
+config SOC_SDM_CLK_SUPPORT_XTAL
+    bool
+    default y
+
 config SOC_SPI_PERIPH_NUM
     int
     default 2

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -101,7 +101,7 @@ typedef enum {
 } soc_rtc_fast_clk_src_t;
 
 // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
-// {[upstream]clock_name}: APB, (BB)PLL, etc.
+// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
 // [attr] - optional: FAST, SLOW, D<divider>, F<freq>
 /**
  * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
@@ -115,7 +115,6 @@ typedef enum {
     SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
     SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
     // For digital domain: peripherals, WIFI, BLE
-    SOC_MOD_CLK_APB,                           /*!< APB_CLK is highly dependent on the CPU_CLK source */    // TODO: IDF-6343 This should be removed on ESP32C6! Impacts on all following peripheral drivers!
     SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
     SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
     SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from PLL, and has a fixed frequency of 240MHz */
@@ -124,7 +123,7 @@ typedef enum {
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
 } soc_module_clk_t;
 
-//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
 
 /**
  * @brief Type of SYSTIMER clock source
@@ -286,22 +285,40 @@ typedef enum {
     I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
 } soc_periph_i2c_clk_src_t;
 
-//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
 
 /**
  * @brief Array initializer for all supported clock sources of SDM
  */
-#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
+#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
 
 /**
  * @brief Sigma Delta Modulator clock source
  */
 typedef enum {
-    SDM_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
-    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
+    SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
+    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
 } soc_periph_sdm_clk_src_t;
 
-//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Glitch Filter
+ */
+#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Glitch filter clock source
+ */
+
+typedef enum {
+    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
+} soc_periph_glitch_filter_clk_src_t;
+
+//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
 /**
  * @brief Array initializer for all supported clock sources of TWAI

components/soc/esp32c6/include/soc/soc_caps.h

@@ -159,6 +159,8 @@
 #define SOC_GPIO_PIN_COUNT                 31
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
+#define SOC_GPIO_FILTER_CLK_SUPPORT_XTAL 1
+#define SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M 1
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1
@@ -310,8 +312,10 @@
 #define SOC_SHA_SUPPORT_SHA256          (1)
 
 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-#define SOC_SDM_GROUPS             1U
-#define SOC_SDM_CHANNELS_PER_GROUP 4
+#define SOC_SDM_GROUPS               1U
+#define SOC_SDM_CHANNELS_PER_GROUP   4
+#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
+#define SOC_SDM_CLK_SUPPORT_XTAL     1
 
 // TODO: IDF-5334 (Copy from esp32c3, need check)
 /*-------------------------- SPI CAPS ----------------------------------------*/