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Merge branch 'feature/i2c_support_on_esp8684_esp32h2' into 'master'

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i2c: support i2c on esp32c2 and esp32h2

Closes IDF-3918

See merge request espressif/esp-idf!16444
This commit is contained in:
Kevin (Lao Kaiyao)
2022-02-28 13:59:02 +08:00
parent 44e5ac2c59 cf353c505a
commit cc1d89ebba
44 changed files with 565 additions and 670 deletions
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194
components/soc/esp32c2/include/soc/i2c_struct.h
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@@ -784,195 +784,29 @@ typedef union {
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
/** Type of comd register
* I2C command register 0~7
*/
typedef union {
struct {
/** command0 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 0. It consists of three parts:
/** command : R/W; bitpos: [13:0]; default: 0;
* This is the content of command. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* When command 0 is done in I2C Master mode, this bit changes to high
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* When command is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 1. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* When command 1 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 2. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* When command 2 is done in I2C Master mode, this bit changes to high
* Level.
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 3. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* When command 3 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 4. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* When command 4 is done in I2C Master mode, this bit changes to high
* level.
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 5. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* When command 5 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 6. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* When command 6 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* This is the content of command 7. It consists of three parts:
* op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more
* Information.
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* When command 7 is done in I2C Master mode, this bit changes to high level.
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@@ -1040,14 +874,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
volatile i2c_clk_conf_reg_t clk_conf;
volatile i2c_comd0_reg_t comd0;
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@@ -1060,7 +887,6 @@ typedef struct {
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");

2
components/soc/esp32c2/include/soc/soc_caps.h
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@@ -116,7 +116,7 @@
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// TODO IDF-3918
// ESP32-C2 has 1 I2C
#define SOC_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */