alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-11-04 06:11:06 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'change/update_gdma_register_esp32c61' into 'master'

Browse Source 
change(dma): update gdma register of esp32c61

See merge request espressif/esp-idf!36028
This commit is contained in:
morris
2025-01-08 23:55:13 +08:00
parent 5700288433 876a747048
commit cc9fb5bd5e
5 changed files with 677 additions and 493 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
components/esp_hw_support/test_apps/dma/main/test_gdma.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -76,14 +76,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
channel_config.sibling_chan = NULL; channel_config.sibling_chan = NULL;
TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0])); TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0]));
TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); gdma_trigger_t fake_ahb_trigger1 = {
.periph = 1,
.bus_id = SOC_GDMA_BUS_AHB,
.instance_id = 0,
};
gdma_trigger_t fake_ahb_trigger2 = {
.periph = 2,
.bus_id = SOC_GDMA_BUS_AHB,
.instance_id = 1,
};
TEST_ESP_OK(gdma_connect(tx_channels[0], fake_ahb_trigger1));
// can't connect multiple channels to the same peripheral // can't connect multiple channels to the same peripheral
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0))); TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_ahb_trigger1));
TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); TEST_ESP_OK(gdma_connect(tx_channels[1], fake_ahb_trigger2));
TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
// but rx and tx can connect to the same peripheral // but rx and tx can connect to the same peripheral
TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); TEST_ESP_OK(gdma_connect(rx_channels[0], fake_ahb_trigger1));
TEST_ESP_OK(gdma_connect(rx_channels[1], fake_ahb_trigger2));
for (int i = 0; i < 2; i++) { for (int i = 0; i < 2; i++) {
TEST_ESP_OK(gdma_disconnect(tx_channels[i])); TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
TEST_ESP_OK(gdma_disconnect(rx_channels[i])); TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
@@ -135,14 +145,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
channel_config.sibling_chan = NULL; channel_config.sibling_chan = NULL;
TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0])); TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0]));
TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); gdma_trigger_t fake_axi_trigger1 = {
.periph = 1,
.bus_id = SOC_GDMA_BUS_AXI,
.instance_id = 0,
};
gdma_trigger_t fake_axi_trigger2 = {
.periph = 2,
.bus_id = SOC_GDMA_BUS_AXI,
.instance_id = 1,
};
TEST_ESP_OK(gdma_connect(tx_channels[0], fake_axi_trigger1));
// can't connect multiple channels to the same peripheral // can't connect multiple channels to the same peripheral
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2))); TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_axi_trigger1));
TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); TEST_ESP_OK(gdma_connect(tx_channels[1], fake_axi_trigger2));
TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
// but rx and tx can connect to the same peripheral // but rx and tx can connect to the same peripheral
TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0))); TEST_ESP_OK(gdma_connect(rx_channels[0], fake_axi_trigger1));
TEST_ESP_OK(gdma_connect(rx_channels[1], fake_axi_trigger2));
for (int i = 0; i < 2; i++) { for (int i = 0; i < 2; i++) {
TEST_ESP_OK(gdma_disconnect(tx_channels[i])); TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
TEST_ESP_OK(gdma_disconnect(rx_channels[i])); TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
@@ -366,7 +386,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]")
{ {
test_gdma_m2m_mode(false); test_gdma_m2m_mode(false);
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION
// test again with retention // test again with retention
test_gdma_m2m_mode(true); test_gdma_m2m_mode(true);
#endif #endif
@@ -384,7 +404,7 @@ static bool test_gdma_m2m_unalgined_rx_eof_callback(gdma_channel_handle_t dma_ch
BaseType_t task_woken = pdFALSE; BaseType_t task_woken = pdFALSE;
test_gdma_context_t *user_ctx = (test_gdma_context_t*)user_data; test_gdma_context_t *user_ctx = (test_gdma_context_t*)user_data;
for (int i = 0; i < 3; i++) { for (int i = 0; i < 3; i++) {
if(user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) { if (user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) {
TEST_ESP_OK(esp_cache_msync(user_ctx->align_array->aligned_buffer[i].aligned_buffer, ALIGN_UP(user_ctx->align_array->aligned_buffer[i].length, user_ctx->split_alignment), ESP_CACHE_MSYNC_FLAG_DIR_M2C)); TEST_ESP_OK(esp_cache_msync(user_ctx->align_array->aligned_buffer[i].aligned_buffer, ALIGN_UP(user_ctx->align_array->aligned_buffer[i].length, user_ctx->split_alignment), ESP_CACHE_MSYNC_FLAG_DIR_M2C));
} }
} }
@@ -471,7 +491,7 @@ static void test_gdma_m2m_unalgined_buffer_test(uint8_t *dst_data, uint8_t *src_
// validate the destination data // validate the destination data
for (int i = 0; i < data_length; i++) { for (int i = 0; i < data_length; i++) {
TEST_ASSERT_EQUAL(i % 256 , dst_data[i + offset_len]); TEST_ASSERT_EQUAL(i % 256, dst_data[i + offset_len]);
} }
free(stash_buffer); free(stash_buffer);

2
components/hal/esp32c61/include/hal/ahb_dma_ll.h
View File

@@ -27,7 +27,7 @@ extern "C" {
#define GDMA_LL_TX_EVENT_MASK (0x3F) #define GDMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode // any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31) #define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFE75)
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F) #define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) #define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)

2
components/soc/esp32c61/include/soc/gdma_channel.h
View File

@@ -9,7 +9,6 @@
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) #define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
@@ -20,7 +19,6 @@
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY #define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB #define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB

667
components/soc/esp32c61/register/soc/ahb_dma_reg.h
View File

File diff suppressed because it is too large Load Diff

445
components/soc/esp32c61/register/soc/ahb_dma_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,7 +12,7 @@ extern "C" {
/** Group: Interrupt Registers */ /** Group: Interrupt Registers */
/** Type of in_int_raw_chn register /** Type of in_int_raw_chn register
* Raw interrupt status of RX channel 0 * RX channel n raw interrupt status register
*/ */
typedef union { typedef union {
struct { struct {
@@ -50,7 +50,7 @@ typedef union {
} ahb_dma_in_int_raw_chn_reg_t; } ahb_dma_in_int_raw_chn_reg_t;
/** Type of in_int_st_chn register /** Type of in_int_st_chn register
* Masked interrupt status of RX channel 0 * RX channel n masked interrupt status register
*/ */
typedef union { typedef union {
struct { struct {
@@ -88,7 +88,7 @@ typedef union {
} ahb_dma_in_int_st_chn_reg_t; } ahb_dma_in_int_st_chn_reg_t;
/** Type of in_int_ena_chn register /** Type of in_int_ena_chn register
* Interrupt enable bits of RX channel 0 * RX channel n interrupt enable register
*/ */
typedef union { typedef union {
struct { struct {
@@ -126,7 +126,7 @@ typedef union {
} ahb_dma_in_int_ena_chn_reg_t; } ahb_dma_in_int_ena_chn_reg_t;
/** Type of in_int_clr_chn register /** Type of in_int_clr_chn register
* Interrupt clear bits of RX channel 0 * RX channel n interrupt clear register
*/ */
typedef union { typedef union {
struct { struct {
@@ -164,7 +164,7 @@ typedef union {
} ahb_dma_in_int_clr_chn_reg_t; } ahb_dma_in_int_clr_chn_reg_t;
/** Type of out_int_raw_chn register /** Type of out_int_raw_chn register
* Raw interrupt status of TX channel 0 * TX channel n raw interrupt status register
*/ */
typedef union { typedef union {
struct { struct {
@@ -198,7 +198,7 @@ typedef union {
} ahb_dma_out_int_raw_chn_reg_t; } ahb_dma_out_int_raw_chn_reg_t;
/** Type of out_int_st_chn register /** Type of out_int_st_chn register
* Masked interrupt status of TX channel 0 * TX channel n masked interrupt status register
*/ */
typedef union { typedef union {
struct { struct {
@@ -232,7 +232,7 @@ typedef union {
} ahb_dma_out_int_st_chn_reg_t; } ahb_dma_out_int_st_chn_reg_t;
/** Type of out_int_ena_chn register /** Type of out_int_ena_chn register
* Interrupt enable bits of TX channel 0 * TX channel n interrupt enable register
*/ */
typedef union { typedef union {
struct { struct {
@@ -266,7 +266,7 @@ typedef union {
} ahb_dma_out_int_ena_chn_reg_t; } ahb_dma_out_int_ena_chn_reg_t;
/** Type of out_int_clr_chn register /** Type of out_int_clr_chn register
* Interrupt clear bits of TX channel 0 * TX channel n interrupt clear register
*/ */
typedef union { typedef union {
struct { struct {
@@ -300,27 +300,6 @@ typedef union {
} ahb_dma_out_int_clr_chn_reg_t; } ahb_dma_out_int_clr_chn_reg_t;
/** Group: Debug Registers */
/** Type of ahb_test register
* reserved
*/
typedef union {
struct {
/** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
* reserved
*/
uint32_t ahb_testmode:3;
uint32_t reserved_3:1;
/** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
uint32_t ahb_testaddr:2;
uint32_t reserved_6:26;
};
uint32_t val;
} ahb_dma_ahb_test_reg_t;
/** Group: Configuration Registers */ /** Group: Configuration Registers */
/** Type of misc_conf register /** Type of misc_conf register
* Miscellaneous register * Miscellaneous register
@@ -333,13 +312,15 @@ typedef union {
uint32_t ahbm_rst_inter:1; uint32_t ahbm_rst_inter:1;
uint32_t reserved_1:1; uint32_t reserved_1:1;
/** arb_pri_dis : R/W; bitpos: [2]; default: 0; /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
* Configures whether or not to disable the fixed-priority channel arbitration.\\0: * Configures whether to disable the priority arbitration.
* Enable\\1: Disable\\ * 0: Enable
* 1: Disable
*/ */
uint32_t arb_pri_dis:1; uint32_t arb_pri_dis:1;
/** clk_en : R/W; bitpos: [3]; default: 0; /** clk_en : R/W; bitpos: [3]; default: 0;
* Configures clock gating.\\0: Support clock only when the application writes * Configures AHB DMA clock gating.
* registers.\\ 1: Always force the clock on for registers.\\ * 0: Support clock only when the application writes registers
* 1: Always force the clock on for registers
*/ */
uint32_t clk_en:1; uint32_t clk_en:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -348,37 +329,44 @@ typedef union {
} ahb_dma_misc_conf_reg_t; } ahb_dma_misc_conf_reg_t;
/** Type of in_conf0_chn register /** Type of in_conf0_chn register
* Configuration register 0 of RX channel 0 * Configuration register 0 of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** in_rst_chn : R/W; bitpos: [0]; default: 0; /** in_rst_chn : R/W; bitpos: [0]; default: 0;
* Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. * Write 1 and then 0 to reset RX channel n FSM and RX FIFO pointer.
*/ */
uint32_t in_rst_chn:1; uint32_t in_rst_chn:1;
/** in_loop_test_chn : R/W; bitpos: [1]; default: 0; /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
* Reserved. * Configures the owner bit value for inlink write-back.
*/ */
uint32_t in_loop_test_chn:1; uint32_t in_loop_test_chn:1;
/** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable INCR burst transfer for RX channel n to read * Configures whether to enable INCR burst transfer for RX channel n to read
* descriptors.\\0: Disable\\1: Enable\\ * descriptors.
* 0: Disable
* 1: Enable
*/ */
uint32_t indscr_burst_en_chn:1; uint32_t indscr_burst_en_chn:1;
uint32_t reserved_3:1; uint32_t reserved_3:1;
/** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable memory-to-memory data transfer.\\0: Disable\\1: * Configures whether to enable memory-to-memory data transfer.
* Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t mem_trans_en_chn:1; uint32_t mem_trans_en_chn:1;
/** in_etm_en_chn : R/W; bitpos: [5]; default: 0; /** in_etm_en_chn : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable ETM control for RX channeln.\\0: Disable\\1: * Configures whether to enable ETM control for RX channeln.
* Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t in_etm_en_chn:1; uint32_t in_etm_en_chn:1;
/** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0; /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0;
* Configures max burst size for Rx channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10: * Configures maximum burst length for RX channeln.
* incr8\\ 2'b11: reserved\\ * 0: SINGLE
* 1: INCR4
* 2: INCR8
* 3: Reserved
*/ */
uint32_t in_data_burst_mode_sel_chn:2; uint32_t in_data_burst_mode_sel_chn:2;
uint32_t reserved_8:24; uint32_t reserved_8:24;
@@ -387,14 +375,15 @@ typedef union {
} ahb_dma_in_conf0_chn_reg_t; } ahb_dma_in_conf0_chn_reg_t;
/** Type of in_conf1_chn register /** Type of in_conf1_chn register
* Configuration register 1 of RX channel 0 * Configuration register 1 of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
uint32_t reserved_0:12; uint32_t reserved_0:12;
/** in_check_owner_chn : R/W; bitpos: [12]; default: 0; /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
* Configures whether or not to enable owner bit check for RX channel n.\\0: * Configures whether to enable owner bit check for RX channel n.
* Disable\\1: Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t in_check_owner_chn:1; uint32_t in_check_owner_chn:1;
uint32_t reserved_13:19; uint32_t reserved_13:19;
@@ -403,17 +392,18 @@ typedef union {
} ahb_dma_in_conf1_chn_reg_t; } ahb_dma_in_conf1_chn_reg_t;
/** Type of in_pop_chn register /** Type of in_pop_chn register
* Pop control register of RX channel 0 * Pop control register of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
* Represents the data popped from AHB_DMA FIFO. * Represents the data popped from AHB DMA RX FIFO.
*/ */
uint32_t infifo_rdata_chn:12; uint32_t infifo_rdata_chn:12;
/** infifo_pop_chn : WT; bitpos: [12]; default: 0; /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
* Configures whether or not to pop data from AHB_DMA FIFO.\\0: Invalid. No effect\\1: * Configures whether to pop data from AHB DMA RX FIFO.
* Pop\\ * 0: Invalid. No effect
* 1: Pop
*/ */
uint32_t infifo_pop_chn:1; uint32_t infifo_pop_chn:1;
uint32_t reserved_13:19; uint32_t reserved_13:19;
@@ -422,32 +412,39 @@ typedef union {
} ahb_dma_in_pop_chn_reg_t; } ahb_dma_in_pop_chn_reg_t;
/** Type of in_link_chn register /** Type of in_link_chn register
* Linked list descriptor configuration and control register of RX channel 0 * Linked list descriptor configuration and control register of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
* Configures whether or not to return to current receive descriptor's address when * Configures whether to return to the current receive descriptor's address when there
* there are some errors in current receiving data.\\0: Not return\\1: Return\\ * are some errors in current receiving data.
* 0: Not return
* 1: Return
*/ */
uint32_t inlink_auto_ret_chn:1; uint32_t inlink_auto_ret_chn:1;
/** inlink_stop_chn : WT; bitpos: [1]; default: 0; /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
* Configures whether or not to stop AHB_DMA's RX channel n from receiving data.\\0: * Configures whether to stop RX channel n from receiving data.
* Invalid. No effect\\1: Stop\\ * 0: Invalid. No effect
* 1: Stop
*/ */
uint32_t inlink_stop_chn:1; uint32_t inlink_stop_chn:1;
/** inlink_start_chn : WT; bitpos: [2]; default: 0; /** inlink_start_chn : WT; bitpos: [2]; default: 0;
* Configures whether or not to enable AHB_DMA's RX channel n for data transfer.\\0: * Configures whether to enable RX channel n for data transfer.
* Disable\\1: Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t inlink_start_chn:1; uint32_t inlink_start_chn:1;
/** inlink_restart_chn : WT; bitpos: [3]; default: 0; /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
* Configures whether or not to restart RX channel n for AHB_DMA transfer.\\0: * Configures whether to restart RX channel n for AHB DMA transfer.
* Invalid. No effect\\1: Restart\\ * 0: Invalid. No effect
* 1: Restart
*/ */
uint32_t inlink_restart_chn:1; uint32_t inlink_restart_chn:1;
/** inlink_park_chn : RO; bitpos: [4]; default: 1; /** inlink_park_chn : RO; bitpos: [4]; default: 1;
* Represents the status of the receive descriptor's FSM.\\0: Running\\1: Idle\\ * Represents the status of the receive descriptor's FSM.
* 0: Running
* 1: Idle
*/ */
uint32_t inlink_park_chn:1; uint32_t inlink_park_chn:1;
uint32_t reserved_5:27; uint32_t reserved_5:27;
@@ -455,15 +452,74 @@ typedef union {
uint32_t val; uint32_t val;
} ahb_dma_in_link_chn_reg_t; } ahb_dma_in_link_chn_reg_t;
/** Type of out_conf0_chn register
* Configuration register 0 of TX channel n
*/
typedef union {
struct {
/** out_rst_chn : R/W; bitpos: [0]; default: 0;
* Configures the reset state of TX channel n FSM and TX FIFO pointer.
* 0: Release reset
* 1: Reset
*/
uint32_t out_rst_chn:1;
/** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
* Configures the owner bit value for outlink write-back.
*/
uint32_t out_loop_test_chn:1;
/** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
* Configures whether to enable automatic outlink write-back when all the data in TX
* FIFO has been transmitted.
* 0: Disable
* 1: Enable
*/
uint32_t out_auto_wrback_chn:1;
/** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
* Configures when to generate EOF flag.
* 0: EOF flag for TX channel n is generated when data to be transmitted has been
* pushed into FIFO in AHB DMA.
* 1: EOF flag for TX channel n is generated when data to be transmitted has been
* popped from FIFO in AHB DMA.
*/
uint32_t out_eof_mode_chn:1;
/** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
* Configures whether to enable INCR burst transfer for TX channel n reading
* descriptors.
* 0: Disable
* 1: Enable
*/
uint32_t outdscr_burst_en_chn:1;
uint32_t reserved_5:1;
/** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
* Configures whether to enable ETM control for TX channel n.
* 0: Disable
* 1: Enable
*/
uint32_t out_etm_en_chn:1;
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0;
* Configures maximum burst length for TX channeln.
* 0: SINGLE
* 1: INCR4
* 2: INCR8
* 3: Reserved
*/
uint32_t out_data_burst_mode_sel_chn:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_chn_reg_t;
/** Type of out_conf1_chn register /** Type of out_conf1_chn register
* Configuration register 1 of TX channel 0 * Configuration register 1 of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
uint32_t reserved_0:12; uint32_t reserved_0:12;
/** out_check_owner_chn : R/W; bitpos: [12]; default: 0; /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
* Configures whether or not to enable owner bit check for TX channel n.\\0: * Configures whether to enable owner bit check for TX channel n.
* Disable\\1: Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t out_check_owner_chn:1; uint32_t out_check_owner_chn:1;
uint32_t reserved_13:19; uint32_t reserved_13:19;
@@ -472,17 +528,18 @@ typedef union {
} ahb_dma_out_conf1_chn_reg_t; } ahb_dma_out_conf1_chn_reg_t;
/** Type of out_push_chn register /** Type of out_push_chn register
* Push control register of TX channel 0 * Push control register of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
* Configures the data that need to be pushed into AHB_DMA FIFO. * Represents the data that need to be pushed into AHB DMA TX FIFO.
*/ */
uint32_t outfifo_wdata_chn:9; uint32_t outfifo_wdata_chn:9;
/** outfifo_push_chn : WT; bitpos: [9]; default: 0; /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
* Configures whether or not to push data into AHB_DMA FIFO.\\0: Invalid. No * Configures whether to push data into AHB DMA TX FIFO.
* effect\\1: Push\\ * 0: Invalid. No effect
* 1: Push
*/ */
uint32_t outfifo_push_chn:1; uint32_t outfifo_push_chn:1;
uint32_t reserved_10:22; uint32_t reserved_10:22;
@@ -491,27 +548,32 @@ typedef union {
} ahb_dma_out_push_chn_reg_t; } ahb_dma_out_push_chn_reg_t;
/** Type of out_link_chn register /** Type of out_link_chn register
* Linked list descriptor configuration and control register of TX channel 0 * Linked list descriptor configuration and control register of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_stop_chn : WT; bitpos: [0]; default: 0; /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
* Configures whether or not to stop AHB_DMA's TX channel n from transmitting * Configures whether to stop TX channel n from transmitting data.
* data.\\0: Invalid. No effect\\1: Stop\\ * 0: Invalid. No effect
* 1: Stop
*/ */
uint32_t outlink_stop_chn:1; uint32_t outlink_stop_chn:1;
/** outlink_start_chn : WT; bitpos: [1]; default: 0; /** outlink_start_chn : WT; bitpos: [1]; default: 0;
* Configures whether or not to enable AHB_DMA's TX channel n for data transfer.\\0: * Configures whether to enable TX channel n for data transfer.
* Disable\\1: Enable\\ * 0: Disable
* 1: Enable
*/ */
uint32_t outlink_start_chn:1; uint32_t outlink_start_chn:1;
/** outlink_restart_chn : WT; bitpos: [2]; default: 0; /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
* Configures whether or not to restart TX channel n for AHB_DMA transfer.\\0: * Configures whether to restart TX channel n for AHB DMA transfer.
* Invalid. No effect\\1: Restart\\ * 0: Invalid. No effect
* 1: Restart
*/ */
uint32_t outlink_restart_chn:1; uint32_t outlink_restart_chn:1;
/** outlink_park_chn : RO; bitpos: [3]; default: 1; /** outlink_park_chn : RO; bitpos: [3]; default: 1;
* Represents the status of the transmit descriptor's FSM.\\0: Running\\1: Idle\\ * Represents the status of the transmit descriptor's FSM.
* 0: Running
* 1: Idle
*/ */
uint32_t outlink_park_chn:1; uint32_t outlink_park_chn:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -519,61 +581,14 @@ typedef union {
uint32_t val; uint32_t val;
} ahb_dma_out_link_chn_reg_t; } ahb_dma_out_link_chn_reg_t;
/** Type of out_conf0_chn register
* Configuration register 0 of TX channel 1
*/
typedef union {
struct {
/** out_rst_chn : R/W; bitpos: [0]; default: 0;
* Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer.\\0:
* Release reset\\1: Reset\\
*/
uint32_t out_rst_chn:1;
/** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
* Reserved.
*/
uint32_t out_loop_test_chn:1;
/** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable automatic outlink write-back when all the data
* in TX FIFO has been transmitted.\\0: Disable\\1: Enable\\
*/
uint32_t out_auto_wrback_chn:1;
/** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
* Configures when to generate EOF flag.\\0: EOF flag for TX channel n is generated
* when data to be transmitted has been pushed into FIFO in AHB_DMA.\\ 1: EOF flag for
* TX channel n is generated when data to be transmitted has been popped from FIFO in
* AHB_DMA.\\
*/
uint32_t out_eof_mode_chn:1;
/** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable INCR burst transfer for TX channel n reading
* descriptors.\\0: Disable\\1: Enable\\
*/
uint32_t outdscr_burst_en_chn:1;
uint32_t reserved_5:1;
/** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
* Configures whether or not to enable ETM control for TX channel n.\\0: Disable\\1:
* Enable\\
*/
uint32_t out_etm_en_chn:1;
uint32_t reserved_7:1;
/** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0;
* Configures max burst size for TX channeln.\\2'b00: single\\ 2'b01: incr4\\ 2'b10:
* incr8\\ 2'b11: reserved\\
*/
uint32_t out_data_burst_mode_sel_chn:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_chn_reg_t;
/** Type of tx_ch_arb_weigh_chn register /** Type of tx_ch_arb_weigh_chn register
* TX channel 0 arbitration weight configuration register * TX channel n arbitration weight configuration register
*/ */
typedef union { typedef union {
struct { struct {
/** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
* Configures the weight(i.e the number of tokens) of TX channeln * Configures the weight (i.e the number of tokens) of TX channeln.
* Value range: 0 ~ 15.
*/ */
uint32_t tx_ch_arb_weigh_chn:4; uint32_t tx_ch_arb_weigh_chn:4;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -582,12 +597,14 @@ typedef union {
} ahb_dma_tx_ch_arb_weigh_chn_reg_t; } ahb_dma_tx_ch_arb_weigh_chn_reg_t;
/** Type of tx_arb_weigh_opt_dir_chn register /** Type of tx_arb_weigh_opt_dir_chn register
* TX channel 0 weight arbitration optimization enable register * TX channel n weight arbitration optimization enable register
*/ */
typedef union { typedef union {
struct { struct {
/** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
* reserved * Configures whether to enable weight optimization for TX channel n.
* 0: Disable
* 1: Enable
*/ */
uint32_t tx_arb_weigh_opt_dir_chn:1; uint32_t tx_arb_weigh_opt_dir_chn:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -596,12 +613,13 @@ typedef union {
} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t; } ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
/** Type of rx_ch_arb_weigh_chn register /** Type of rx_ch_arb_weigh_chn register
* RX channel 0 arbitration weight configuration register * RX channel n arbitration weight configuration register
*/ */
typedef union { typedef union {
struct { struct {
/** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
* Configures the weight(i.e the number of tokens) of RX channeln * Configures the weight (i.e the number of tokens) of RX channeln.
* Value range: 0 ~ 15.
*/ */
uint32_t rx_ch_arb_weigh_chn:4; uint32_t rx_ch_arb_weigh_chn:4;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -610,12 +628,14 @@ typedef union {
} ahb_dma_rx_ch_arb_weigh_chn_reg_t; } ahb_dma_rx_ch_arb_weigh_chn_reg_t;
/** Type of rx_arb_weigh_opt_dir_chn register /** Type of rx_arb_weigh_opt_dir_chn register
* RX channel 0 weight arbitration optimization enable register * RX channel n weight arbitration optimization enable register
*/ */
typedef union { typedef union {
struct { struct {
/** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
* reserved * Configures whether to enable weight optimization for RX channel n.
* 0: Disable
* 1: Enable
*/ */
uint32_t rx_arb_weigh_opt_dir_chn:1; uint32_t rx_arb_weigh_opt_dir_chn:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -624,12 +644,12 @@ typedef union {
} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; } ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
/** Type of in_link_addr_chn register /** Type of in_link_addr_chn register
* Link list descriptor address configuration of RX channel 0 * Linked list descriptor configuration register of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
* Configures the 32 bits of the first receive descriptor's address. * Represents the first receive descriptor's address.
*/ */
uint32_t inlink_addr_chn:32; uint32_t inlink_addr_chn:32;
}; };
@@ -637,12 +657,12 @@ typedef union {
} ahb_dma_in_link_addr_chn_reg_t; } ahb_dma_in_link_addr_chn_reg_t;
/** Type of out_link_addr_chn register /** Type of out_link_addr_chn register
* Link list descriptor address configuration of TX channel 0 * Linked list descriptor configuration register of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
* Configures the 32 bits of the first receive descriptor's address. * Represents the first transmit descriptor's address.
*/ */
uint32_t outlink_addr_chn:32; uint32_t outlink_addr_chn:32;
}; };
@@ -709,7 +729,9 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** weight_en_tx : R/W; bitpos: [0]; default: 0; /** weight_en_tx : R/W; bitpos: [0]; default: 0;
* Configures whether to enable weight arbitration for TX.\\0: Disable\\1: Enable\\ * Configures whether to enable weight arbitration for TX.
* 0: Disable
* 1: Enable
*/ */
uint32_t weight_en_tx:1; uint32_t weight_en_tx:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -723,7 +745,9 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** weight_en_rx : R/W; bitpos: [0]; default: 0; /** weight_en_rx : R/W; bitpos: [0]; default: 0;
* Configures whether to enable weight arbitration for RX.\\0: Disable\\1: Enable\\ * Configures whether to enable weight arbitration for RX.
* 0: Disable
* 1: Enable
*/ */
uint32_t weight_en_rx:1; uint32_t weight_en_rx:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -749,16 +773,20 @@ typedef union {
/** Group: Status Registers */ /** Group: Status Registers */
/** Type of infifo_status_chn register /** Type of infifo_status_chn register
* Receive FIFO status of RX channel 0 * RX channel n FIFO status
*/ */
typedef union { typedef union {
struct { struct {
/** infifo_full_chn : RO; bitpos: [0]; default: 1; /** infifo_full_chn : RO; bitpos: [0]; default: 1;
* Represents whether or not L1 RX FIFO is full.\\0: Not Full\\1: Full\\ * Represents whether L1 RX FIFO is full.
* 0: Not Full
* 1: Full
*/ */
uint32_t infifo_full_chn:1; uint32_t infifo_full_chn:1;
/** infifo_empty_chn : RO; bitpos: [1]; default: 1; /** infifo_empty_chn : RO; bitpos: [1]; default: 1;
* Represents whether or not L1 RX FIFO is empty.\\0: Not empty\\1: Empty\\ * Represents whether L1 RX FIFO is empty.
* 0: Not empty
* 1: Empty
*/ */
uint32_t infifo_empty_chn:1; uint32_t infifo_empty_chn:1;
uint32_t reserved_2:6; uint32_t reserved_2:6;
@@ -768,23 +796,23 @@ typedef union {
uint32_t infifo_cnt_chn:7; uint32_t infifo_cnt_chn:7;
uint32_t reserved_15:8; uint32_t reserved_15:8;
/** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
* reserved * Reserved.
*/ */
uint32_t in_remain_under_1b_chn:1; uint32_t in_remain_under_1b_chn:1;
/** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
* reserved * Reserved.
*/ */
uint32_t in_remain_under_2b_chn:1; uint32_t in_remain_under_2b_chn:1;
/** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
* reserved * Reserved.
*/ */
uint32_t in_remain_under_3b_chn:1; uint32_t in_remain_under_3b_chn:1;
/** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
* reserved * Reserved.
*/ */
uint32_t in_remain_under_4b_chn:1; uint32_t in_remain_under_4b_chn:1;
/** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0;
* reserved * Reserved.
*/ */
uint32_t in_buf_hungry_chn:1; uint32_t in_buf_hungry_chn:1;
uint32_t reserved_28:4; uint32_t reserved_28:4;
@@ -793,21 +821,23 @@ typedef union {
} ahb_dma_infifo_status_chn_reg_t; } ahb_dma_infifo_status_chn_reg_t;
/** Type of in_state_chn register /** Type of in_state_chn register
* Receive status of RX channel 0 * RX channel n status
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
* Represents the address of the lower 18 bits of the next receive descriptor to be * Represents the lower 18 bits of the next receive descriptor address that is
* processed. * pre-read (but not processed yet). If the current receive descriptor is the last
* descriptor, then this field represents the address of the current receive
* descriptor.
*/ */
uint32_t inlink_dscr_addr_chn:18; uint32_t inlink_dscr_addr_chn:18;
/** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
* reserved * Reserved.
*/ */
uint32_t in_dscr_state_chn:2; uint32_t in_dscr_state_chn:2;
/** in_state_chn : RO; bitpos: [22:20]; default: 0; /** in_state_chn : RO; bitpos: [22:20]; default: 0;
* reserved * Reserved.
*/ */
uint32_t in_state_chn:3; uint32_t in_state_chn:3;
uint32_t reserved_23:9; uint32_t reserved_23:9;
@@ -816,7 +846,7 @@ typedef union {
} ahb_dma_in_state_chn_reg_t; } ahb_dma_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register /** Type of in_suc_eof_des_addr_chn register
* Receive descriptor address when EOF occurs on RX channel 0 * Receive descriptor address when EOF occurs on RX channel n
*/ */
typedef union { typedef union {
struct { struct {
@@ -830,7 +860,7 @@ typedef union {
} ahb_dma_in_suc_eof_des_addr_chn_reg_t; } ahb_dma_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register /** Type of in_err_eof_des_addr_chn register
* Receive descriptor address when errors occur of RX channel 0 * Receive descriptor address when errors occur of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
@@ -844,13 +874,14 @@ typedef union {
} ahb_dma_in_err_eof_des_addr_chn_reg_t; } ahb_dma_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register /** Type of in_dscr_chn register
* Current receive descriptor address of RX channel 0 * Address of the next receive descriptor pointed by the current pre-read receive
* descriptor on RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next receive descriptor x+1 pointed by the current * Represents the address of the next receive descriptor x+1 pointed by the current
* receive descriptor that has already been fetched. * receive descriptor that is pre-read.
*/ */
uint32_t inlink_dscr_chn:32; uint32_t inlink_dscr_chn:32;
}; };
@@ -858,13 +889,12 @@ typedef union {
} ahb_dma_in_dscr_chn_reg_t; } ahb_dma_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register /** Type of in_dscr_bf0_chn register
* The last receive descriptor address of RX channel 0 * Address of the current pre-read receive descriptor on RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the current receive descriptor x that has already been * Represents the address of the current receive descriptor x that is pre-read.
* fetched.
*/ */
uint32_t inlink_dscr_bf0_chn:32; uint32_t inlink_dscr_bf0_chn:32;
}; };
@@ -872,13 +902,12 @@ typedef union {
} ahb_dma_in_dscr_bf0_chn_reg_t; } ahb_dma_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register /** Type of in_dscr_bf1_chn register
* The second-to-last receive descriptor address of RX channel 0 * Address of the previous pre-read receive descriptor on RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the previous receive descriptor x-1 that has already been * Represents the address of the previous receive descriptor x-1 that is pre-read.
* fetched.
*/ */
uint32_t inlink_dscr_bf1_chn:32; uint32_t inlink_dscr_bf1_chn:32;
}; };
@@ -886,12 +915,12 @@ typedef union {
} ahb_dma_in_dscr_bf1_chn_reg_t; } ahb_dma_in_dscr_bf1_chn_reg_t;
/** Type of in_done_des_addr_chn register /** Type of in_done_des_addr_chn register
* RX_done Inlink descriptor address of RX channel 0 * Address of the completed inlink descriptor on RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the inlink descriptor when this descriptor is completed . * Represents the address of the inlink descriptor when this descriptor is completed.
*/ */
uint32_t in_done_des_addr_chn:32; uint32_t in_done_des_addr_chn:32;
}; };
@@ -899,16 +928,20 @@ typedef union {
} ahb_dma_in_done_des_addr_chn_reg_t; } ahb_dma_in_done_des_addr_chn_reg_t;
/** Type of outfifo_status_chn register /** Type of outfifo_status_chn register
* Transmit FIFO status of TX channel 0 * TX channel n FIFO status
*/ */
typedef union { typedef union {
struct { struct {
/** outfifo_full_chn : RO; bitpos: [0]; default: 0; /** outfifo_full_chn : RO; bitpos: [0]; default: 0;
* Represents whether or not L1 TX FIFO is full.\\0: Not Full\\1: Full\\ * Represents whether L1 TX FIFO is full.
* 0: Not Full
* 1: Full
*/ */
uint32_t outfifo_full_chn:1; uint32_t outfifo_full_chn:1;
/** outfifo_empty_chn : RO; bitpos: [1]; default: 1; /** outfifo_empty_chn : RO; bitpos: [1]; default: 1;
* Represents whether or not L1 TX FIFO is empty.\\0: Not empty\\1: Empty\\ * Represents whether L1 TX FIFO is empty.
* 0: Not empty
* 1: Empty
*/ */
uint32_t outfifo_empty_chn:1; uint32_t outfifo_empty_chn:1;
uint32_t reserved_2:6; uint32_t reserved_2:6;
@@ -939,21 +972,23 @@ typedef union {
} ahb_dma_outfifo_status_chn_reg_t; } ahb_dma_outfifo_status_chn_reg_t;
/** Type of out_state_chn register /** Type of out_state_chn register
* Transmit status of TX channel 0 * TX channel n status
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
* Represents the lower 18 bits of the address of the next transmit descriptor to be * Represents the lower 18 bits of the next transmit descriptor address that is
* processed. * pre-read (but not processed yet). If the current transmit descriptor is the last
* descriptor, then this field represents the address of the current transmit
* descriptor.
*/ */
uint32_t outlink_dscr_addr_chn:18; uint32_t outlink_dscr_addr_chn:18;
/** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
* reserved * Reserved.
*/ */
uint32_t out_dscr_state_chn:2; uint32_t out_dscr_state_chn:2;
/** out_state_chn : RO; bitpos: [22:20]; default: 0; /** out_state_chn : RO; bitpos: [22:20]; default: 0;
* reserved * Reserved.
*/ */
uint32_t out_state_chn:3; uint32_t out_state_chn:3;
uint32_t reserved_23:9; uint32_t reserved_23:9;
@@ -962,7 +997,7 @@ typedef union {
} ahb_dma_out_state_chn_reg_t; } ahb_dma_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register /** Type of out_eof_des_addr_chn register
* Transmit descriptor address when EOF occurs on TX channel 0 * Transmit descriptor address when EOF occurs on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
@@ -976,7 +1011,7 @@ typedef union {
} ahb_dma_out_eof_des_addr_chn_reg_t; } ahb_dma_out_eof_des_addr_chn_reg_t;
/** Type of out_eof_bfr_des_addr_chn register /** Type of out_eof_bfr_des_addr_chn register
* The last transmit descriptor address when EOF occurs on TX channel 0 * The last transmit descriptor address when EOF occurs on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
@@ -990,13 +1025,14 @@ typedef union {
} ahb_dma_out_eof_bfr_des_addr_chn_reg_t; } ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
/** Type of out_dscr_chn register /** Type of out_dscr_chn register
* Current transmit descriptor address of TX channel 0 * Address of the next transmit descriptor pointed by the current pre-read transmit
* descriptor on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the next transmit descriptor y+1 pointed by the current * Represents the address of the next transmit descriptor y+1 pointed by the current
* transmit descriptor that has already been fetched. * transmit descriptor that is pre-read.
*/ */
uint32_t outlink_dscr_chn:32; uint32_t outlink_dscr_chn:32;
}; };
@@ -1004,13 +1040,12 @@ typedef union {
} ahb_dma_out_dscr_chn_reg_t; } ahb_dma_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register /** Type of out_dscr_bf0_chn register
* The last transmit descriptor address of TX channel 0 * Address of the current pre-read transmit descriptor on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the current transmit descriptor y that has already been * Represents the address of the current transmit descriptor y that is pre-read.
* fetched.
*/ */
uint32_t outlink_dscr_bf0_chn:32; uint32_t outlink_dscr_bf0_chn:32;
}; };
@@ -1018,13 +1053,12 @@ typedef union {
} ahb_dma_out_dscr_bf0_chn_reg_t; } ahb_dma_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register /** Type of out_dscr_bf1_chn register
* The second-to-last transmit descriptor address of TX channel 0 * Address of the previous pre-read transmit descriptor on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
* Represents the address of the previous transmit descriptor y-1 that has already * Represents the address of the previous transmit descriptor y-1 that is pre-read.
* been fetched.
*/ */
uint32_t outlink_dscr_bf1_chn:32; uint32_t outlink_dscr_bf1_chn:32;
}; };
@@ -1032,7 +1066,7 @@ typedef union {
} ahb_dma_out_dscr_bf1_chn_reg_t; } ahb_dma_out_dscr_bf1_chn_reg_t;
/** Type of out_done_des_addr_chn register /** Type of out_done_des_addr_chn register
* TX done outlink descriptor address of TX channel 0 * Address of the completed outlink descriptor on TX channel n
*/ */
typedef union { typedef union {
struct { struct {
@@ -1047,13 +1081,14 @@ typedef union {
/** Group: Priority Registers */ /** Group: Priority Registers */
/** Type of in_pri_chn register /** Type of in_pri_chn register
* Priority register of RX channel 0 * Priority register of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
* Configures the priority of RX channel n.The larger of the value, the higher of the * Configures the priority of RX channel n. The larger the value, the higher the
* priority. * priority.
* Value range: 0 ~ 5
*/ */
uint32_t rx_pri_chn:4; uint32_t rx_pri_chn:4;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -1062,13 +1097,14 @@ typedef union {
} ahb_dma_in_pri_chn_reg_t; } ahb_dma_in_pri_chn_reg_t;
/** Type of out_pri_chn register /** Type of out_pri_chn register
* Priority register of TX channel 0 * Priority register of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
* Configures the priority of TX channel n.The larger of the value, the higher of the * Configures the priority of TX channel n. The larger the value, the higher the
* priority. * priority.
* Value range: 0 ~ 5
*/ */
uint32_t tx_pri_chn:4; uint32_t tx_pri_chn:4;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -1077,16 +1113,23 @@ typedef union {
} ahb_dma_out_pri_chn_reg_t; } ahb_dma_out_pri_chn_reg_t;
/** Group: Peripheral Select Registers */ /** Group: Peripheral Selection Registers */
/** Type of in_peri_sel_chn register /** Type of in_peri_sel_chn register
* Peripheral selection register of RX channel 0 * Peripheral selection register of RX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
* Configures the peripheral connected to RX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: * Configures the peripheral connected to RX channel n.
* UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ * 0: Dummy
* 10: Dummy\\ 11~15: Dummy\\ * 1: GP-SPI
* 2: Dummy
* 3: I2S
* 4 ~ 6: Dummy
* 7: SHA
* 8: ADC
* 9 ~ 15: Dummy
* 16 ~ 63: Invalid
*/ */
uint32_t peri_in_sel_chn:6; uint32_t peri_in_sel_chn:6;
uint32_t reserved_6:26; uint32_t reserved_6:26;
@@ -1095,14 +1138,21 @@ typedef union {
} ahb_dma_in_peri_sel_chn_reg_t; } ahb_dma_in_peri_sel_chn_reg_t;
/** Type of out_peri_sel_chn register /** Type of out_peri_sel_chn register
* Peripheral selection register of TX channel 0 * Peripheral selection register of TX channel n
*/ */
typedef union { typedef union {
struct { struct {
/** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
* Configures the peripheral connected to TX channel n.\\ 0: Dummy\\ 1: SPI2\\ 2: * Configures the peripheral connected to TX channel n.
* UHCI0\\ 3: I2S0\\ 4: Dummy\\ 5: Dummy\\ 6: AES\\ 7: SHA\\ 8: ADC_DAC\\ 9: PARL_IO\\ * 0: Dummy
* 10: Dummy\\ 11~15: Dummy\\ * 1: GP-SPI
* 2: Dummy
* 3: I2S
* 4 ~ 6: Dummy
* 7: SHA
* 8: ADC
* 9 ~ 15: Dummy
* 16 ~ 63: Invalid
*/ */
uint32_t peri_out_sel_chn:6; uint32_t peri_out_sel_chn:6;
uint32_t reserved_6:26; uint32_t reserved_6:26;
@@ -1184,8 +1234,7 @@ typedef struct {
volatile ahb_dma_in_int_chn_reg_t in_intr[2]; volatile ahb_dma_in_int_chn_reg_t in_intr[2];
uint32_t reserved_020[4]; uint32_t reserved_020[4];
volatile ahb_dma_out_int_chn_reg_t out_intr[2]; volatile ahb_dma_out_int_chn_reg_t out_intr[2];
uint32_t reserved_050[4]; uint32_t reserved_050[5];
volatile ahb_dma_ahb_test_reg_t ahb_test;
volatile ahb_dma_misc_conf_reg_t misc_conf; volatile ahb_dma_misc_conf_reg_t misc_conf;
volatile ahb_dma_date_reg_t date; volatile ahb_dma_date_reg_t date;
uint32_t reserved_06c; uint32_t reserved_06c;