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gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3

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When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible
to set pins 18 and 19 as GPIOs. This commit solves this by manually
disabling USB JTAG when using pins 18 or 19.
The functions shall use `gpio_hal_iomux_func_sel` instead of
`PIN_FUNC_SELELECT`.
This commit is contained in:
Omar Chebib
2021-03-16 10:55:05 +08:00
parent f13b10a17b
commit cd79f3907d
35 changed files with 201 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
components/esp32/test/test_ahb_arb.c
View File

@@ -4,6 +4,7 @@
#include <stdlib.h>
#include "esp32/rom/lldesc.h"
#include "driver/periph_ctrl.h"
#include "hal/gpio_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -36,16 +37,16 @@ static void lcdIfaceInit(void)
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));

5
components/esp32/test/test_fastbus.c
View File

@@ -10,6 +10,7 @@
#include "unity.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"
#include "hal/gpio_hal.h"
#include "driver/gpio.h"
@@ -104,8 +105,8 @@ TEST_CASE("Fast I/O bus test", "[hw][ignore]")
}
gpio_pullup_dis(10);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD);
int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S);
WRITE_PERI_REG(UART_CONF1_REG(1), reg_val);

21
components/esp32/test/test_unal_dma.c
View File

@@ -5,6 +5,7 @@
#include <string.h>
#include "esp32/rom/lldesc.h"
#include "driver/periph_ctrl.h"
#include "hal/gpio_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -32,16 +33,16 @@ static void dmaMemcpy(void *in, void *out, int len)
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));