alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-30 19:19:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'refactor/riscv_interrupt' into 'master'

Browse Source 
refactor(riscv): Refactor crosscore interrupts and core interrupt code

Closes IDF-5720, DOC-5177, and IDF-7899

See merge request espressif/esp-idf!27845
This commit is contained in:
Omar Chebib
2024-01-19 10:51:04 +08:00
parent 0d9d004d00 102d5bbf72
commit cdde05335e
49 changed files with 1161 additions and 297 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c
View File

@@ -9,7 +9,7 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/interrupt_reg.h"
#include "hal/crosscore_int_ll.h"
#include "hal/systimer_hal.h"
#include "hal/systimer_ll.h"
#include "riscv/rvruntime-frames.h"
@@ -184,6 +184,9 @@ void IRAM_ATTR vPortReleaseLock( portMUX_TYPE *lock )
void vPortYield(void)
{
// TODO: IDF-8113
const int core_id = 0;
if (uxInterruptNesting) {
vPortYieldFromISR();
} else {
@@ -199,7 +202,7 @@ void vPortYield(void)
for an instant yield, and if that happens then the WFI would be
waiting for the next interrupt to occur...)
*/
while (uxSchedulerRunning && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) {}
while (uxSchedulerRunning && crosscore_int_ll_get_state(core_id) != 0) {}
}
}
@@ -283,7 +286,7 @@ BaseType_t xPortStartScheduler(void)
/* Setup the hardware to generate the tick. */
vPortSetupTimer();
esprv_intc_int_set_threshold(1); /* set global INTC masking level */
esprv_int_set_threshold(1); /* set global INTC masking level */
rv_utils_intr_global_enable();
vPortYield();

12
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
View File

@@ -46,6 +46,7 @@
#include "riscv/rv_utils.h"
#include "riscv/interrupt.h"
#include "esp_private/crosscore_int.h"
#include "hal/crosscore_int_ll.h"
#include "esp_attr.h"
#include "esp_system.h"
#include "esp_intr_alloc.h"
@@ -144,7 +145,7 @@ BaseType_t xPortStartScheduler(void)
/* Setup the hardware to generate the tick. */
vPortSetupTimer();
esprv_intc_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
rv_utils_intr_global_enable();
vPortYield();
@@ -626,13 +627,6 @@ void vPortExitCritical(void)
void vPortYield(void)
{
BaseType_t coreID = xPortGetCoreID();
int system_cpu_int_reg;
#if !CONFIG_IDF_TARGET_ESP32P4
system_cpu_int_reg = SYSTEM_CPU_INTR_FROM_CPU_0_REG;
#else
system_cpu_int_reg = HP_SYSTEM_CPU_INT_FROM_CPU_0_REG;
#endif /* !CONFIG_IDF_TARGET_ESP32P4 */
if (port_uxInterruptNesting[coreID]) {
vPortYieldFromISR();
@@ -648,7 +642,7 @@ void vPortYield(void)
for an instant yield, and if that happens then the WFI would be
waiting for the next interrupt to occur...)
*/
while (port_xSchedulerRunning[coreID] && port_uxCriticalNesting[coreID] == 0 && REG_READ(system_cpu_int_reg + 4 * coreID) != 0) {}
while (port_xSchedulerRunning[coreID] && port_uxCriticalNesting[coreID] == 0 && crosscore_int_ll_get_state(coreID) != 0) {}
}
}

4
components/freertos/test_apps/freertos/performance/test_isr_latency.c
View File

@@ -23,8 +23,8 @@
#define TEST_CLR_INT_MASK(mask) xt_set_intclear(mask)
#elif CONFIG_IDF_TARGET_ARCH_RISCV
#include "riscv/interrupt.h"
#define TEST_SET_INT_MASK(mask) esprv_intc_int_enable(mask)
#define TEST_CLR_INT_MASK(mask) esprv_intc_int_disable(mask)
#define TEST_SET_INT_MASK(mask) esprv_int_enable(mask)
#define TEST_CLR_INT_MASK(mask) esprv_int_disable(mask)
#endif
#ifndef __riscv // TODO: IDF-4416