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Merge branch 'feature/esp32h21_gdma_support' into 'master'

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feat(gdma): add GDMA support for ESP32H21

Closes IDF-11603 and IDF-11604

See merge request espressif/esp-idf!37063
This commit is contained in:
Song Ruo Jing
2025-02-27 14:07:52 +08:00
parent f02812544e a4a28b57a3
commit ce3d603e05
12 changed files with 964 additions and 296 deletions
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123
components/soc/esp32h21/gdma_periph.c Normal file
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@@ -0,0 +1,123 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gdma_periph.h"
#include "soc/gdma_reg.h"
const gdma_signal_conn_t gdma_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
},
[1] = {
.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
},
[2] = {
.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
}
}
}
}
};
#if SOC_PAU_SUPPORTED
/* GDMA Channel (Group0, Pair0) Registers Context
Include: GDMA_MISC_CONF_REG /
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
*/
#define G0P0_RETENTION_REGS_CNT 13
#define G0P0_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH0_REG
static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
G0P0_RETENTION_REGS_CNT, 0, 0, \
g0p0_regs_map[0], g0p0_regs_map[1], \
g0p0_regs_map[2], g0p0_regs_map[3]), \
.owner = GDMA_RETENTION_ENTRY
},
};
/* GDMA Channel (Group0, Pair1) Registers Context
Include: GDMA_MISC_CONF_REG /
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
*/
#define G0P1_RETENTION_REGS_CNT 13
#define G0P1_RETENTION_MAP_BASE GDMA_IN_INT_ENA_CH1_REG
static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
G0P1_RETENTION_REGS_CNT, 0, 0, \
g0p1_regs_map[0], g0p1_regs_map[1], \
g0p1_regs_map[2], g0p1_regs_map[3]), \
.owner = GDMA_RETENTION_ENTRY
},
};
/* GDMA Channel (Group0, Pair2) Registers Context
Include: GDMA_MISC_CONF_REG /
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
*/
#define G0P2_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
#define G0P2_RETENTION_REGS_CNT_1 7
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = GDMA_RETENTION_ENTRY
},
[1] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
.owner = GDMA_RETENTION_ENTRY
},
};
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
[0] = {
[0] = {
gdma_g0p0_regs_retention,
ARRAY_SIZE(gdma_g0p0_regs_retention),
SLEEP_RETENTION_MODULE_GDMA_CH0,
},
[1] = {
gdma_g0p1_regs_retention,
ARRAY_SIZE(gdma_g0p1_regs_retention),
SLEEP_RETENTION_MODULE_GDMA_CH1,
},
[2] = {
gdma_g0p2_regs_retention,
ARRAY_SIZE(gdma_g0p2_regs_retention),
SLEEP_RETENTION_MODULE_GDMA_CH2,
}
}
};
#endif

20
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
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@@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_AHB_GDMA_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@@ -219,6 +231,10 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_AHB_GDMA_VERSION
int
default 1
config SOC_GDMA_NUM_GROUPS_MAX
int
default 1
@@ -227,6 +243,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ETM_GROUPS
int
default 1

27
components/soc/esp32h21/include/soc/gdma_channel.h
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@@ -1,5 +1,30 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB

12
components/soc/esp32h21/include/soc/soc_caps.h
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@@ -21,13 +21,13 @@
// #define SOC_ANA_CMPR_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11621
#define SOC_UART_SUPPORTED 1
// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603
// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
// #define SOC_IEEE802154_BLE_ONLY 1
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11616
// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32H21] IDF-11624
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
@@ -176,11 +176,11 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
// #define SOC_AHB_GDMA_VERSION 1U
#define SOC_AHB_GDMA_VERSION 1U
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-11604
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups

255
components/soc/esp32h21/register/soc/gdma_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -472,48 +472,48 @@ typedef union {
uint32_t val;
} gdma_in_link_chn_reg_t;
/** Type of out_conf0_ch0 register
* Configure 0 register of Tx channel 0.
/** Type of out_conf0_chn register
* Configure 0 register of Tx channel n.
*/
typedef union {
struct {
/** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
* This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
/** out_rst_chn : R/W; bitpos: [0]; default: 0;
* This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer.
*/
uint32_t out_rst_ch0:1;
/** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
uint32_t out_rst_chn:1;
/** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t out_loop_test_ch0:1;
/** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
uint32_t out_loop_test_chn:1;
/** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
* Set this bit to enable automatic outlink-writeback when all the data in tx buffer
* has been transmitted.
*/
uint32_t out_auto_wrback_ch0:1;
/** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
* EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
uint32_t out_auto_wrback_chn:1;
/** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
* EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is
* generated when data need to transmit has been popped from FIFO in DMA
*/
uint32_t out_eof_mode_ch0:1;
/** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
uint32_t out_eof_mode_chn:1;
/** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link
* descriptor when accessing internal SRAM.
*/
uint32_t outdscr_burst_en_ch0:1;
/** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data
uint32_t outdscr_burst_en_chn:1;
/** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data
* when accessing internal SRAM.
*/
uint32_t out_data_burst_en_ch0:1;
/** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
* Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm
uint32_t out_data_burst_en_chn:1;
/** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
* Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm
* task.
*/
uint32_t out_etm_en_ch0:1;
uint32_t out_etm_en_chn:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_out_conf0_ch0_reg_t;
} gdma_out_conf0_chn_reg_t;
/** Type of out_conf1_chn register
* Configure 1 register of Tx channel n.
@@ -580,49 +580,6 @@ typedef union {
uint32_t val;
} gdma_out_link_chn_reg_t;
/** Type of out_conf0_chn register
* Configure 0 register of Tx channel n.
*/
typedef union {
struct {
/** out_rst_chn : R/W; bitpos: [0]; default: 0;
* This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer.
*/
uint32_t out_rst_chn:1;
/** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t out_loop_test_chn:1;
/** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
* Set this bit to enable automatic outlink-writeback when all the data in tx buffer
* has been transmitted.
*/
uint32_t out_auto_wrback_chn:1;
/** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
* EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is
* generated when data need to transmit has been popped from FIFO in DMA
*/
uint32_t out_eof_mode_chn:1;
/** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link
* descriptor when accessing internal SRAM.
*/
uint32_t outdscr_burst_en_chn:1;
/** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data
* when accessing internal SRAM.
*/
uint32_t out_data_burst_en_chn:1;
/** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
* Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm
* task.
*/
uint32_t out_etm_en_chn:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_out_conf0_chn_reg_t;
/** Group: Version Registers */
/** Type of date register
@@ -966,123 +923,73 @@ typedef union {
typedef struct {
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0;
volatile gdma_in_int_st_chn_reg_t in_int_st_ch0;
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0;
volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0;
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1;
volatile gdma_in_int_st_chn_reg_t in_int_st_ch1;
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1;
volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1;
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2;
volatile gdma_in_int_st_chn_reg_t in_int_st_ch2;
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2;
volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2;
volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0;
volatile gdma_out_int_st_chn_reg_t out_int_st_ch0;
volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0;
volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0;
volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1;
volatile gdma_out_int_st_chn_reg_t out_int_st_ch1;
volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1;
volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1;
volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2;
volatile gdma_out_int_st_chn_reg_t out_int_st_ch2;
volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2;
volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2;
volatile gdma_in_int_raw_chn_reg_t raw;
volatile gdma_in_int_st_chn_reg_t st;
volatile gdma_in_int_ena_chn_reg_t ena;
volatile gdma_in_int_clr_chn_reg_t clr;
} gdma_in_int_chn_reg_t;
typedef struct {
volatile gdma_out_int_raw_chn_reg_t raw;
volatile gdma_out_int_st_chn_reg_t st;
volatile gdma_out_int_ena_chn_reg_t ena;
volatile gdma_out_int_clr_chn_reg_t clr;
} gdma_out_int_chn_reg_t;
typedef struct {
volatile gdma_in_conf0_chn_reg_t in_conf0;
volatile gdma_in_conf1_chn_reg_t in_conf1;
volatile gdma_infifo_status_chn_reg_t infifo_status;
volatile gdma_in_pop_chn_reg_t in_pop;
volatile gdma_in_link_chn_reg_t in_link;
volatile gdma_in_state_chn_reg_t in_state;
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile gdma_in_dscr_chn_reg_t in_dscr;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile gdma_in_pri_chn_reg_t in_pri;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel;
} gdma_in_chn_reg_t;
typedef struct {
volatile gdma_out_conf0_chn_reg_t out_conf0;
volatile gdma_out_conf1_chn_reg_t out_conf1;
volatile gdma_outfifo_status_chn_reg_t outfifo_status;
volatile gdma_out_push_chn_reg_t out_push;
volatile gdma_out_link_chn_reg_t out_link;
volatile gdma_out_state_chn_reg_t out_state;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
volatile gdma_out_dscr_chn_reg_t out_dscr;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
volatile gdma_out_pri_chn_reg_t out_pri;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel;
} gdma_out_chn_reg_t;
typedef struct {
volatile gdma_in_chn_reg_t in;
uint32_t reserved_in[11];
volatile gdma_out_chn_reg_t out;
uint32_t reserved_out[11];
} gdma_chn_reg_t;
typedef struct gdma_dev_s {
volatile gdma_in_int_chn_reg_t in_intr[3];
volatile gdma_out_int_chn_reg_t out_intr[3];
volatile gdma_ahb_test_reg_t ahb_test;
volatile gdma_misc_conf_reg_t misc_conf;
volatile gdma_date_reg_t date;
uint32_t reserved_06c;
volatile gdma_in_conf0_chn_reg_t in_conf0_ch0;
volatile gdma_in_conf1_chn_reg_t in_conf1_ch0;
volatile gdma_infifo_status_chn_reg_t infifo_status_ch0;
volatile gdma_in_pop_chn_reg_t in_pop_ch0;
volatile gdma_in_link_chn_reg_t in_link_ch0;
volatile gdma_in_state_chn_reg_t in_state_ch0;
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
volatile gdma_in_dscr_chn_reg_t in_dscr_ch0;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
volatile gdma_in_pri_chn_reg_t in_pri_ch0;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
uint32_t reserved_0a4[11];
volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0;
volatile gdma_out_conf1_chn_reg_t out_conf1_ch0;
volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0;
volatile gdma_out_push_chn_reg_t out_push_ch0;
volatile gdma_out_link_chn_reg_t out_link_ch0;
volatile gdma_out_state_chn_reg_t out_state_ch0;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
volatile gdma_out_dscr_chn_reg_t out_dscr_ch0;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
volatile gdma_out_pri_chn_reg_t out_pri_ch0;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
uint32_t reserved_104[11];
volatile gdma_in_conf0_chn_reg_t in_conf0_ch1;
volatile gdma_in_conf1_chn_reg_t in_conf1_ch1;
volatile gdma_infifo_status_chn_reg_t infifo_status_ch1;
volatile gdma_in_pop_chn_reg_t in_pop_ch1;
volatile gdma_in_link_chn_reg_t in_link_ch1;
volatile gdma_in_state_chn_reg_t in_state_ch1;
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
volatile gdma_in_dscr_chn_reg_t in_dscr_ch1;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
volatile gdma_in_pri_chn_reg_t in_pri_ch1;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
uint32_t reserved_164[11];
volatile gdma_out_conf0_chn_reg_t out_conf0_ch1;
volatile gdma_out_conf1_chn_reg_t out_conf1_ch1;
volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1;
volatile gdma_out_push_chn_reg_t out_push_ch1;
volatile gdma_out_link_chn_reg_t out_link_ch1;
volatile gdma_out_state_chn_reg_t out_state_ch1;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
volatile gdma_out_dscr_chn_reg_t out_dscr_ch1;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
volatile gdma_out_pri_chn_reg_t out_pri_ch1;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
uint32_t reserved_1c4[11];
volatile gdma_in_conf0_chn_reg_t in_conf0_ch2;
volatile gdma_in_conf1_chn_reg_t in_conf1_ch2;
volatile gdma_infifo_status_chn_reg_t infifo_status_ch2;
volatile gdma_in_pop_chn_reg_t in_pop_ch2;
volatile gdma_in_link_chn_reg_t in_link_ch2;
volatile gdma_in_state_chn_reg_t in_state_ch2;
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
volatile gdma_in_dscr_chn_reg_t in_dscr_ch2;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
volatile gdma_in_pri_chn_reg_t in_pri_ch2;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2;
uint32_t reserved_224[11];
volatile gdma_out_conf0_chn_reg_t out_conf0_ch2;
volatile gdma_out_conf1_chn_reg_t out_conf1_ch2;
volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2;
volatile gdma_out_push_chn_reg_t out_push_ch2;
volatile gdma_out_link_chn_reg_t out_link_ch2;
volatile gdma_out_state_chn_reg_t out_state_ch2;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2;
volatile gdma_out_dscr_chn_reg_t out_dscr_ch2;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
volatile gdma_out_pri_chn_reg_t out_pri_ch2;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2;
volatile gdma_chn_reg_t channel[3];
} gdma_dev_t;
extern gdma_dev_t GDMA;
#ifndef __cplusplus
_Static_assert(sizeof(gdma_dev_t) == 0x284, "Invalid size of gdma_dev_t structure");
_Static_assert(sizeof(gdma_dev_t) == 0x2B0, "Invalid size of gdma_dev_t structure");
#endif
#ifdef __cplusplus

140
components/soc/esp32h21/register/soc/hp_apm_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,7 +14,7 @@ extern "C" {
/** HP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_BASE + 0x0)
#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0)
/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1;
* Region filter enable
*/
@@ -26,7 +26,7 @@ extern "C" {
/** HP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_BASE + 0x4)
#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4)
/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
@@ -38,7 +38,7 @@ extern "C" {
/** HP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_BASE + 0x8)
#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8)
/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
@@ -50,7 +50,7 @@ extern "C" {
/** HP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_BASE + 0xc)
#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc)
/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -118,7 +118,7 @@ extern "C" {
/** HP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_BASE + 0x10)
#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10)
/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
@@ -130,7 +130,7 @@ extern "C" {
/** HP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_BASE + 0x14)
#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14)
/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
@@ -142,7 +142,7 @@ extern "C" {
/** HP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_BASE + 0x18)
#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18)
/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -210,7 +210,7 @@ extern "C" {
/** HP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_BASE + 0x1c)
#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c)
/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
@@ -222,7 +222,7 @@ extern "C" {
/** HP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_BASE + 0x20)
#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20)
/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
@@ -234,7 +234,7 @@ extern "C" {
/** HP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_BASE + 0x24)
#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24)
/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -302,7 +302,7 @@ extern "C" {
/** HP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_BASE + 0x28)
#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28)
/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
@@ -314,7 +314,7 @@ extern "C" {
/** HP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_BASE + 0x2c)
#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c)
/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
@@ -326,7 +326,7 @@ extern "C" {
/** HP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_BASE + 0x30)
#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30)
/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -394,7 +394,7 @@ extern "C" {
/** HP_APM_REGION4_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_BASE + 0x34)
#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34)
/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region4
*/
@@ -406,7 +406,7 @@ extern "C" {
/** HP_APM_REGION4_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_BASE + 0x38)
#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38)
/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region4
*/
@@ -418,7 +418,7 @@ extern "C" {
/** HP_APM_REGION4_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_BASE + 0x3c)
#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c)
/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -486,7 +486,7 @@ extern "C" {
/** HP_APM_REGION5_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_BASE + 0x40)
#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40)
/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region5
*/
@@ -498,7 +498,7 @@ extern "C" {
/** HP_APM_REGION5_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_BASE + 0x44)
#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44)
/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region5
*/
@@ -510,7 +510,7 @@ extern "C" {
/** HP_APM_REGION5_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_BASE + 0x48)
#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48)
/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -578,7 +578,7 @@ extern "C" {
/** HP_APM_REGION6_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_BASE + 0x4c)
#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c)
/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region6
*/
@@ -590,7 +590,7 @@ extern "C" {
/** HP_APM_REGION6_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_BASE + 0x50)
#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50)
/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region6
*/
@@ -602,7 +602,7 @@ extern "C" {
/** HP_APM_REGION6_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_BASE + 0x54)
#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54)
/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -670,7 +670,7 @@ extern "C" {
/** HP_APM_REGION7_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_BASE + 0x58)
#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58)
/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region7
*/
@@ -682,7 +682,7 @@ extern "C" {
/** HP_APM_REGION7_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_BASE + 0x5c)
#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c)
/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region7
*/
@@ -694,7 +694,7 @@ extern "C" {
/** HP_APM_REGION7_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_BASE + 0x60)
#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60)
/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -762,7 +762,7 @@ extern "C" {
/** HP_APM_REGION8_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_BASE + 0x64)
#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64)
/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region8
*/
@@ -774,7 +774,7 @@ extern "C" {
/** HP_APM_REGION8_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_BASE + 0x68)
#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68)
/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region8
*/
@@ -786,7 +786,7 @@ extern "C" {
/** HP_APM_REGION8_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_BASE + 0x6c)
#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c)
/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -854,7 +854,7 @@ extern "C" {
/** HP_APM_REGION9_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_BASE + 0x70)
#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70)
/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region9
*/
@@ -866,7 +866,7 @@ extern "C" {
/** HP_APM_REGION9_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_BASE + 0x74)
#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74)
/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region9
*/
@@ -878,7 +878,7 @@ extern "C" {
/** HP_APM_REGION9_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_BASE + 0x78)
#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78)
/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -946,7 +946,7 @@ extern "C" {
/** HP_APM_REGION10_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_BASE + 0x7c)
#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c)
/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region10
*/
@@ -958,7 +958,7 @@ extern "C" {
/** HP_APM_REGION10_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_BASE + 0x80)
#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80)
/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region10
*/
@@ -970,7 +970,7 @@ extern "C" {
/** HP_APM_REGION10_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_BASE + 0x84)
#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84)
/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1038,7 +1038,7 @@ extern "C" {
/** HP_APM_REGION11_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_BASE + 0x88)
#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88)
/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region11
*/
@@ -1050,7 +1050,7 @@ extern "C" {
/** HP_APM_REGION11_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_BASE + 0x8c)
#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c)
/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region11
*/
@@ -1062,7 +1062,7 @@ extern "C" {
/** HP_APM_REGION11_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_BASE + 0x90)
#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90)
/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1130,7 +1130,7 @@ extern "C" {
/** HP_APM_REGION12_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_BASE + 0x94)
#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94)
/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region12
*/
@@ -1142,7 +1142,7 @@ extern "C" {
/** HP_APM_REGION12_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_BASE + 0x98)
#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98)
/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region12
*/
@@ -1154,7 +1154,7 @@ extern "C" {
/** HP_APM_REGION12_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_BASE + 0x9c)
#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c)
/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1222,7 +1222,7 @@ extern "C" {
/** HP_APM_REGION13_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_BASE + 0xa0)
#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0)
/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region13
*/
@@ -1234,7 +1234,7 @@ extern "C" {
/** HP_APM_REGION13_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_BASE + 0xa4)
#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4)
/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region13
*/
@@ -1246,7 +1246,7 @@ extern "C" {
/** HP_APM_REGION13_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_BASE + 0xa8)
#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8)
/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1314,7 +1314,7 @@ extern "C" {
/** HP_APM_REGION14_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_BASE + 0xac)
#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac)
/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region14
*/
@@ -1326,7 +1326,7 @@ extern "C" {
/** HP_APM_REGION14_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_BASE + 0xb0)
#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0)
/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region14
*/
@@ -1338,7 +1338,7 @@ extern "C" {
/** HP_APM_REGION14_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_BASE + 0xb4)
#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4)
/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1406,7 +1406,7 @@ extern "C" {
/** HP_APM_REGION15_ADDR_START_REG register
* Region address register
*/
#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_BASE + 0xb8)
#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8)
/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region15
*/
@@ -1418,7 +1418,7 @@ extern "C" {
/** HP_APM_REGION15_ADDR_END_REG register
* Region address register
*/
#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_BASE + 0xbc)
#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc)
/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region15
*/
@@ -1430,7 +1430,7 @@ extern "C" {
/** HP_APM_REGION15_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_BASE + 0xc0)
#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0)
/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -1498,7 +1498,7 @@ extern "C" {
/** HP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_BASE + 0xc4)
#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4)
/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
@@ -1531,7 +1531,7 @@ extern "C" {
/** HP_APM_M0_STATUS_REG register
* M0 status register
*/
#define HP_APM_M0_STATUS_REG (DR_REG_HP_BASE + 0xc8)
#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8)
/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -1543,7 +1543,7 @@ extern "C" {
/** HP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_BASE + 0xcc)
#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc)
/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -1555,7 +1555,7 @@ extern "C" {
/** HP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xd0)
#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0)
/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Exception region
*/
@@ -1581,7 +1581,7 @@ extern "C" {
/** HP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xd4)
#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4)
/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -1593,7 +1593,7 @@ extern "C" {
/** HP_APM_M1_STATUS_REG register
* M1 status register
*/
#define HP_APM_M1_STATUS_REG (DR_REG_HP_BASE + 0xd8)
#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8)
/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -1605,7 +1605,7 @@ extern "C" {
/** HP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_BASE + 0xdc)
#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc)
/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -1617,7 +1617,7 @@ extern "C" {
/** HP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xe0)
#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0)
/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Exception region
*/
@@ -1643,7 +1643,7 @@ extern "C" {
/** HP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xe4)
#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4)
/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -1655,7 +1655,7 @@ extern "C" {
/** HP_APM_M2_STATUS_REG register
* M2 status register
*/
#define HP_APM_M2_STATUS_REG (DR_REG_HP_BASE + 0xe8)
#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8)
/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -1667,7 +1667,7 @@ extern "C" {
/** HP_APM_M2_STATUS_CLR_REG register
* M2 status clear register
*/
#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_BASE + 0xec)
#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec)
/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -1679,7 +1679,7 @@ extern "C" {
/** HP_APM_M2_EXCEPTION_INFO0_REG register
* M2 exception_info0 register
*/
#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0xf0)
#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0)
/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Exception region
*/
@@ -1705,7 +1705,7 @@ extern "C" {
/** HP_APM_M2_EXCEPTION_INFO1_REG register
* M2 exception_info1 register
*/
#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0xf4)
#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4)
/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -1717,7 +1717,7 @@ extern "C" {
/** HP_APM_M3_STATUS_REG register
* M3 status register
*/
#define HP_APM_M3_STATUS_REG (DR_REG_HP_BASE + 0xf8)
#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8)
/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -1729,7 +1729,7 @@ extern "C" {
/** HP_APM_M3_STATUS_CLR_REG register
* M3 status clear register
*/
#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_BASE + 0xfc)
#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc)
/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -1741,7 +1741,7 @@ extern "C" {
/** HP_APM_M3_EXCEPTION_INFO0_REG register
* M3 exception_info0 register
*/
#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_BASE + 0x100)
#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100)
/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
* Exception region
*/
@@ -1767,7 +1767,7 @@ extern "C" {
/** HP_APM_M3_EXCEPTION_INFO1_REG register
* M3 exception_info1 register
*/
#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_BASE + 0x104)
#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104)
/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -1779,7 +1779,7 @@ extern "C" {
/** HP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define HP_APM_INT_EN_REG (DR_REG_HP_BASE + 0x108)
#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108)
/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
@@ -1812,7 +1812,7 @@ extern "C" {
/** HP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_BASE + 0x10c)
#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c)
/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
@@ -1824,7 +1824,7 @@ extern "C" {
/** HP_APM_DATE_REG register
* Version register
*/
#define HP_APM_DATE_REG (DR_REG_HP_BASE + 0x7fc)
#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc)
/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/

44
components/soc/esp32h21/register/soc/lp_apm0_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,7 +14,7 @@ extern "C" {
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0)
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
@@ -26,7 +26,7 @@ extern "C" {
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4)
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
@@ -38,7 +38,7 @@ extern "C" {
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8)
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
@@ -50,7 +50,7 @@ extern "C" {
/** LP_APM0_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc)
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -118,7 +118,7 @@ extern "C" {
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10)
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
@@ -130,7 +130,7 @@ extern "C" {
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14)
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
@@ -142,7 +142,7 @@ extern "C" {
/** LP_APM0_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18)
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -210,7 +210,7 @@ extern "C" {
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_BASE + 0x1c)
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
@@ -222,7 +222,7 @@ extern "C" {
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_BASE + 0x20)
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
@@ -234,7 +234,7 @@ extern "C" {
/** LP_APM0_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_BASE + 0x24)
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -302,7 +302,7 @@ extern "C" {
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_BASE + 0x28)
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
@@ -314,7 +314,7 @@ extern "C" {
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_BASE + 0x2c)
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
@@ -326,7 +326,7 @@ extern "C" {
/** LP_APM0_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_BASE + 0x30)
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -394,7 +394,7 @@ extern "C" {
/** LP_APM0_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4)
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
@@ -406,7 +406,7 @@ extern "C" {
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8)
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -418,7 +418,7 @@ extern "C" {
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc)
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -430,7 +430,7 @@ extern "C" {
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0)
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
@@ -456,7 +456,7 @@ extern "C" {
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4)
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -468,7 +468,7 @@ extern "C" {
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_BASE + 0xd8)
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
@@ -480,7 +480,7 @@ extern "C" {
/** LP_APM0_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xdc)
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
@@ -492,7 +492,7 @@ extern "C" {
/** LP_APM0_DATE_REG register
* Version register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_BASE + 0x7fc)
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/

32
components/soc/esp32h21/register/soc/lp_apm_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,7 +14,7 @@ extern "C" {
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0)
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [1:0]; default: 1;
* Region filter enable
*/
@@ -26,7 +26,7 @@ extern "C" {
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4)
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
@@ -38,7 +38,7 @@ extern "C" {
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8)
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
@@ -50,7 +50,7 @@ extern "C" {
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc)
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -118,7 +118,7 @@ extern "C" {
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10)
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
@@ -130,7 +130,7 @@ extern "C" {
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14)
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
@@ -142,7 +142,7 @@ extern "C" {
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18)
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
@@ -210,7 +210,7 @@ extern "C" {
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4)
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
@@ -222,7 +222,7 @@ extern "C" {
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8)
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
@@ -234,7 +234,7 @@ extern "C" {
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc)
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
@@ -246,7 +246,7 @@ extern "C" {
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0)
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [1:0]; default: 0;
* Exception region
*/
@@ -272,7 +272,7 @@ extern "C" {
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4)
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
@@ -284,7 +284,7 @@ extern "C" {
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_BASE + 0xe8)
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
@@ -296,7 +296,7 @@ extern "C" {
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xec)
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
@@ -308,7 +308,7 @@ extern "C" {
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_BASE + 0xfc)
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35680864;
* reg_date
*/