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fix(usb): Fixed missing GPIO drive capability on ESP32-P4
All USB PHYs that share their IOs with GPIOs must set the GPIO's drive capability to maximum.
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@@ -1,12 +1,10 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "soc/gpio_sig_map.h"
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#include "soc/usb_periph.h"
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#include "soc/interrupts.h"
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#include "soc/usb_dwc_periph.h"
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@@ -41,6 +39,11 @@ static const usb_otg_signal_conn_t otg_signals = {
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.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
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};
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static const usb_internal_phy_io_t internal_phy_io = {
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.dp = 20,
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.dm = 19,
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};
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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@@ -48,6 +51,7 @@ const usb_dwc_info_t usb_dwc_info = {
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[0] = {
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.fsls_signals = &fsls_signals,
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.otg_signals = &otg_signals,
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.internal_phy_io = &internal_phy_io,
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.irq = ETS_USB_INTR_SOURCE,
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.irq_2nd_cpu = -1,
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},
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@@ -56,6 +60,7 @@ const usb_dwc_info_t usb_dwc_info = {
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/* ------------------------------- Deprecated ------------------------------- */
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#include "soc/usb_periph.h"
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/*
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Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
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PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
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