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esp_wifi: synchronize Wi-Fi adapter between different chips
Support preferring to allocate Wi-Fi memory from PSRAM on ESP32-S3 Support Wi-Fi TX cache buffer on ESP32-S3
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@@ -40,6 +40,7 @@
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#include "esp_phy_init.h"
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#include "esp32s2/clk.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc.h"
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#include "soc/syscon_reg.h"
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#include "phy_init_data.h"
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#include "driver/periph_ctrl.h"
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@@ -242,7 +243,7 @@ static void semphr_delete_wrapper(void *semphr)
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static void wifi_thread_semphr_free(void* data)
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{
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xSemaphoreHandle *sem = (xSemaphoreHandle*)(data);
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SemaphoreHandle_t *sem = (SemaphoreHandle_t*)(data);
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if (sem) {
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vSemaphoreDelete(sem);
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@@ -253,7 +254,7 @@ static void * wifi_thread_semphr_get_wrapper(void)
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{
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static bool s_wifi_thread_sem_key_init = false;
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static pthread_key_t s_wifi_thread_sem_key;
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xSemaphoreHandle sem = NULL;
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SemaphoreHandle_t sem = NULL;
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if (s_wifi_thread_sem_key_init == false) {
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if (0 != pthread_key_create(&s_wifi_thread_sem_key, wifi_thread_semphr_free)) {
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@@ -455,7 +456,7 @@ static uint32_t esp_clk_slowclk_cal_get_wrapper(void)
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/* The bit width of WiFi light sleep clock calibration is 12 while the one of
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* system is 19. It should shift 19 - 12 = 7.
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*/
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return (esp_clk_slowclk_cal_get() >> 7);
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return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH));
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}
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static void * IRAM_ATTR malloc_internal_wrapper(size_t size)
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@@ -536,7 +537,7 @@ static int coex_wifi_request_wrapper(uint32_t event, uint32_t latency, uint32_t
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#endif
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}
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static int coex_wifi_release_wrapper(uint32_t event)
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static IRAM_ATTR int coex_wifi_release_wrapper(uint32_t event)
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{
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#if CONFIG_SW_COEXIST_ENABLE
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return coex_wifi_release(event);
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