esp_wifi: synchronize Wi-Fi adapter between different chips

Support preferring to allocate Wi-Fi memory from PSRAM on ESP32-S3

Support Wi-Fi TX cache buffer on ESP32-S3
This commit is contained in:
Xia Xiaotian
2021-02-24 16:24:16 +08:00
parent f53c0c5b87
commit ce8b996ca0
11 changed files with 99 additions and 51 deletions

View File

@@ -40,6 +40,7 @@
#include "esp_phy_init.h"
#include "esp32s2/clk.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "soc/syscon_reg.h"
#include "phy_init_data.h"
#include "driver/periph_ctrl.h"
@@ -242,7 +243,7 @@ static void semphr_delete_wrapper(void *semphr)
static void wifi_thread_semphr_free(void* data)
{
xSemaphoreHandle *sem = (xSemaphoreHandle*)(data);
SemaphoreHandle_t *sem = (SemaphoreHandle_t*)(data);
if (sem) {
vSemaphoreDelete(sem);
@@ -253,7 +254,7 @@ static void * wifi_thread_semphr_get_wrapper(void)
{
static bool s_wifi_thread_sem_key_init = false;
static pthread_key_t s_wifi_thread_sem_key;
xSemaphoreHandle sem = NULL;
SemaphoreHandle_t sem = NULL;
if (s_wifi_thread_sem_key_init == false) {
if (0 != pthread_key_create(&s_wifi_thread_sem_key, wifi_thread_semphr_free)) {
@@ -455,7 +456,7 @@ static uint32_t esp_clk_slowclk_cal_get_wrapper(void)
/* The bit width of WiFi light sleep clock calibration is 12 while the one of
* system is 19. It should shift 19 - 12 = 7.
*/
return (esp_clk_slowclk_cal_get() >> 7);
return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH));
}
static void * IRAM_ATTR malloc_internal_wrapper(size_t size)
@@ -536,7 +537,7 @@ static int coex_wifi_request_wrapper(uint32_t event, uint32_t latency, uint32_t
#endif
}
static int coex_wifi_release_wrapper(uint32_t event)
static IRAM_ATTR int coex_wifi_release_wrapper(uint32_t event)
{
#if CONFIG_SW_COEXIST_ENABLE
return coex_wifi_release(event);