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https://github.com/espressif/esp-idf.git
synced 2025-08-09 20:41:14 +00:00
esp8684: rename target to esp32c2
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -31,8 +31,8 @@
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#include "esp32h2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#elif CONFIG_IDF_TARGET_ESP8684
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#include "esp8684/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#endif
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@@ -328,7 +328,7 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st
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icache_state = Cache_Suspend_ICache() << 16;
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dcache_state = Cache_Suspend_DCache();
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*saved_state = icache_state | dcache_state;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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uint32_t icache_state;
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icache_state = Cache_Suspend_ICache() << 16;
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*saved_state = icache_state;
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@@ -354,7 +354,7 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
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#elif CONFIG_IDF_TARGET_ESP32S3
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Cache_Resume_DCache(saved_state & 0xffff);
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Cache_Resume_ICache(saved_state >> 16);
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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Cache_Resume_ICache(saved_state >> 16);
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#endif
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}
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@@ -368,7 +368,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void)
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S2
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bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0);
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#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0);
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#endif
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return result;
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@@ -483,19 +483,19 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
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int i;
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bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
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uint32_t drom0_in_icache = 1;//always 1 in esp32s2
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#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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drom0_in_icache = 0;
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#endif
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if (icache_wrap_enable) {
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP8684_INSTRUCTION_CACHE_LINE_16B
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C2_INSTRUCTION_CACHE_LINE_16B
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icache_wrap_size = 16;
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#else
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icache_wrap_size = 32;
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#endif
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}
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if (dcache_wrap_enable) {
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#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP8684_INSTRUCTION_CACHE_LINE_16B
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#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B || CONFIG_ESP32C3_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32H2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32C2_INSTRUCTION_CACHE_LINE_16B
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dcache_wrap_size = 16;
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#else
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dcache_wrap_size = 32;
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@@ -884,7 +884,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
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}
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#endif
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#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache)
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{
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@@ -926,7 +926,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
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}
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return ESP_OK;
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}
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#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
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#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
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{
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