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feat(efuse): Add flash&psram efuses for S3

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KonstantinKondrashov
2023-07-06 15:27:24 +08:00
parent 0298e6f257
commit cf46ef954f
7 changed files with 210 additions and 20 deletions
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57
components/soc/esp32s3/include/soc/efuse_reg.h
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@@ -816,25 +816,60 @@ extern "C" {
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_S 24
/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0;
* reserved
/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
* Flash capacity
*/
#define EFUSE_RESERVED_1_123 0x0000001FU
#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S)
#define EFUSE_RESERVED_1_123_V 0x0000001FU
#define EFUSE_RESERVED_1_123_S 27
#define EFUSE_FLASH_CAP 0x00000007U
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
#define EFUSE_FLASH_CAP_V 0x00000007U
#define EFUSE_FLASH_CAP_S 27
/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
* Flash temperature
*/
#define EFUSE_FLASH_TEMP 0x00000003U
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
#define EFUSE_FLASH_TEMP_V 0x00000003U
#define EFUSE_FLASH_TEMP_S 30
/** EFUSE_RD_MAC_SPI_SYS_4_REG register
* BLOCK1 data register 4.
*/
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_RESERVED_1_128 : R; bitpos: [12:0]; default: 0;
/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
* Flash vendor
*/
#define EFUSE_FLASH_VENDOR 0x00000007U
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
#define EFUSE_FLASH_VENDOR_V 0x00000007U
#define EFUSE_FLASH_VENDOR_S 0
/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0;
* PSRAM capacity
*/
#define EFUSE_PSRAM_CAP 0x00000003U
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
#define EFUSE_PSRAM_CAP_V 0x00000003U
#define EFUSE_PSRAM_CAP_S 3
/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0;
* PSRAM temperature
*/
#define EFUSE_PSRAM_TEMP 0x00000003U
#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
#define EFUSE_PSRAM_TEMP_V 0x00000003U
#define EFUSE_PSRAM_TEMP_S 5
/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0;
* PSRAM vendor
*/
#define EFUSE_PSRAM_VENDOR 0x00000003U
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
#define EFUSE_PSRAM_VENDOR_S 7
/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_128 0x00001FFFU
#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S)
#define EFUSE_RESERVED_1_128_V 0x00001FFFU
#define EFUSE_RESERVED_1_128_S 0
#define EFUSE_RESERVED_1_137 0x0000000FU
#define EFUSE_RESERVED_1_137_M (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S)
#define EFUSE_RESERVED_1_137_V 0x0000000FU
#define EFUSE_RESERVED_1_137_S 9
/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0;
* BLOCK1 K_RTC_LDO
*/