alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-12-16 04:22:22 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/hw_crc_esp32p4' into 'master'

Browse Source 
feat(gdma): support hardware crc calculation on esp32p4

Closes IDF-7497

See merge request espressif/esp-idf!25307
This commit is contained in:
morris
2023-08-31 14:46:32 +08:00
parent 23ebfd1420 b962fdee89
commit cf61f63bc2
24 changed files with 1005 additions and 110 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -247,6 +247,10 @@ config SOC_AHB_GDMA_VERSION
int
default 2
config SOC_GDMA_SUPPORT_CRC
bool
default y
config SOC_GDMA_NUM_GROUPS_MAX
int
default 2

72
components/soc/esp32p4/include/soc/ahb_dma_reg.h
View File

@@ -3124,7 +3124,7 @@ extern "C" {
#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_S 0
/** AHB_DMA_TX_CRC_WIDTH_CH0_REG register
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3136,13 +3136,13 @@ extern "C" {
#define AHB_DMA_TX_CRC_WIDTH_CH0_M (AHB_DMA_TX_CRC_WIDTH_CH0_V << AHB_DMA_TX_CRC_WIDTH_CH0_S)
#define AHB_DMA_TX_CRC_WIDTH_CH0_V 0x00000003U
#define AHB_DMA_TX_CRC_WIDTH_CH0_S 0
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S 2
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0 (BIT(2))
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH0_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH0_S)
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_V 0x00000001U
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_S 2
/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG register
* This register is used to clear ch0 crc result
@@ -3253,7 +3253,7 @@ extern "C" {
#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_S 0
/** AHB_DMA_TX_CRC_WIDTH_CH1_REG register
* This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
* This register is used to config tx ch1 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3265,13 +3265,13 @@ extern "C" {
#define AHB_DMA_TX_CRC_WIDTH_CH1_M (AHB_DMA_TX_CRC_WIDTH_CH1_V << AHB_DMA_TX_CRC_WIDTH_CH1_S)
#define AHB_DMA_TX_CRC_WIDTH_CH1_V 0x00000003U
#define AHB_DMA_TX_CRC_WIDTH_CH1_S 0
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S 2
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1 (BIT(2))
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH1_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH1_S)
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_V 0x00000001U
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_S 2
/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG register
* This register is used to clear ch1 crc result
@@ -3382,7 +3382,7 @@ extern "C" {
#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_S 0
/** AHB_DMA_TX_CRC_WIDTH_CH2_REG register
* This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
* This register is used to config tx ch2 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3394,13 +3394,13 @@ extern "C" {
#define AHB_DMA_TX_CRC_WIDTH_CH2_M (AHB_DMA_TX_CRC_WIDTH_CH2_V << AHB_DMA_TX_CRC_WIDTH_CH2_S)
#define AHB_DMA_TX_CRC_WIDTH_CH2_V 0x00000003U
#define AHB_DMA_TX_CRC_WIDTH_CH2_S 0
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S 2
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2 (BIT(2))
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH2_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH2_S)
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_V 0x00000001U
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_S 2
/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG register
* This register is used to clear ch2 crc result
@@ -3511,7 +3511,7 @@ extern "C" {
#define AHB_DMA_IN_CRC_INIT_DATA_CH0_S 0
/** AHB_DMA_RX_CRC_WIDTH_CH0_REG register
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3523,13 +3523,13 @@ extern "C" {
#define AHB_DMA_RX_CRC_WIDTH_CH0_M (AHB_DMA_RX_CRC_WIDTH_CH0_V << AHB_DMA_RX_CRC_WIDTH_CH0_S)
#define AHB_DMA_RX_CRC_WIDTH_CH0_V 0x00000003U
#define AHB_DMA_RX_CRC_WIDTH_CH0_S 0
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S 2
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0 (BIT(2))
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH0_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH0_S)
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_V 0x00000001U
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_S 2
/** AHB_DMA_IN_CRC_CLEAR_CH0_REG register
* This register is used to clear ch0 crc result
@@ -3640,7 +3640,7 @@ extern "C" {
#define AHB_DMA_IN_CRC_INIT_DATA_CH1_S 0
/** AHB_DMA_RX_CRC_WIDTH_CH1_REG register
* This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
* This register is used to config rx ch1 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3652,13 +3652,13 @@ extern "C" {
#define AHB_DMA_RX_CRC_WIDTH_CH1_M (AHB_DMA_RX_CRC_WIDTH_CH1_V << AHB_DMA_RX_CRC_WIDTH_CH1_S)
#define AHB_DMA_RX_CRC_WIDTH_CH1_V 0x00000003U
#define AHB_DMA_RX_CRC_WIDTH_CH1_S 0
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S 2
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1 (BIT(2))
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH1_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH1_S)
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_V 0x00000001U
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_S 2
/** AHB_DMA_IN_CRC_CLEAR_CH1_REG register
* This register is used to clear ch1 crc result
@@ -3769,7 +3769,7 @@ extern "C" {
#define AHB_DMA_IN_CRC_INIT_DATA_CH2_S 0
/** AHB_DMA_RX_CRC_WIDTH_CH2_REG register
* This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
* This register is used to config rx ch2 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3781,13 +3781,13 @@ extern "C" {
#define AHB_DMA_RX_CRC_WIDTH_CH2_M (AHB_DMA_RX_CRC_WIDTH_CH2_V << AHB_DMA_RX_CRC_WIDTH_CH2_S)
#define AHB_DMA_RX_CRC_WIDTH_CH2_V 0x00000003U
#define AHB_DMA_RX_CRC_WIDTH_CH2_S 0
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S 2
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2 (BIT(2))
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH2_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH2_S)
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_V 0x00000001U
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_S 2
/** AHB_DMA_IN_CRC_CLEAR_CH2_REG register
* This register is used to clear ch2 crc result

16
components/soc/esp32p4/include/soc/ahb_dma_struct.h
View File

@@ -583,7 +583,7 @@ typedef union {
} ahb_dma_out_crc_init_data_chn_reg_t;
/** Type of tx_crc_width_chn register
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -593,10 +593,10 @@ typedef union {
* reserved
*/
uint32_t tx_crc_width_chn: 2;
/** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
/** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t tx_crc_lautch_flga_chn: 1;
uint32_t tx_crc_latch_flag_chn: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
@@ -724,7 +724,7 @@ typedef union {
} ahb_dma_in_crc_init_data_chn_reg_t;
/** Type of rx_crc_width_chn register
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -734,10 +734,10 @@ typedef union {
* reserved
*/
uint32_t rx_crc_width_chn: 2;
/** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
/** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t rx_crc_lautch_flga_chn: 1;
uint32_t rx_crc_latch_flag_chn: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
@@ -1350,7 +1350,7 @@ typedef struct {
ahb_dma_in_crc_init_data_chn_reg_t crc_init_data;
ahb_dma_rx_crc_width_chn_reg_t crc_width;
ahb_dma_in_crc_clear_chn_reg_t crc_clear;
ahb_dma_in_crc_final_result_chn_reg_t crc_final;
ahb_dma_in_crc_final_result_chn_reg_t crc_final_result;
ahb_dma_rx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
ahb_dma_rx_crc_en_addr_chn_reg_t crc_en_addr;
ahb_dma_rx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
@@ -1369,7 +1369,7 @@ typedef struct {
ahb_dma_tx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
ahb_dma_tx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt_dir;
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
} ahb_dma_out_crc_chn_reg_t;
typedef struct {

72
components/soc/esp32p4/include/soc/axi_dma_reg.h
View File

@@ -803,7 +803,7 @@ extern "C" {
#define AXI_DMA_IN_CRC_INIT_DATA_CH0_S 0
/** AXI_DMA_RX_CRC_WIDTH_CH0_REG register
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -815,13 +815,13 @@ extern "C" {
#define AXI_DMA_RX_CRC_WIDTH_CH0_M (AXI_DMA_RX_CRC_WIDTH_CH0_V << AXI_DMA_RX_CRC_WIDTH_CH0_S)
#define AXI_DMA_RX_CRC_WIDTH_CH0_V 0x00000003U
#define AXI_DMA_RX_CRC_WIDTH_CH0_S 0
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S 2
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0 (BIT(2))
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH0_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH0_S)
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_V 0x00000001U
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_S 2
/** AXI_DMA_IN_CRC_CLEAR_CH0_REG register
* This register is used to clear ch0 crc result
@@ -1687,7 +1687,7 @@ extern "C" {
#define AXI_DMA_IN_CRC_INIT_DATA_CH1_S 0
/** AXI_DMA_RX_CRC_WIDTH_CH1_REG register
* This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
* This register is used to config rx ch1 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -1699,13 +1699,13 @@ extern "C" {
#define AXI_DMA_RX_CRC_WIDTH_CH1_M (AXI_DMA_RX_CRC_WIDTH_CH1_V << AXI_DMA_RX_CRC_WIDTH_CH1_S)
#define AXI_DMA_RX_CRC_WIDTH_CH1_V 0x00000003U
#define AXI_DMA_RX_CRC_WIDTH_CH1_S 0
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S 2
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1 (BIT(2))
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH1_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH1_S)
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_V 0x00000001U
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_S 2
/** AXI_DMA_IN_CRC_CLEAR_CH1_REG register
* This register is used to clear ch1 crc result
@@ -2571,7 +2571,7 @@ extern "C" {
#define AXI_DMA_IN_CRC_INIT_DATA_CH2_S 0
/** AXI_DMA_RX_CRC_WIDTH_CH2_REG register
* This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
* This register is used to config rx ch2 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -2583,13 +2583,13 @@ extern "C" {
#define AXI_DMA_RX_CRC_WIDTH_CH2_M (AXI_DMA_RX_CRC_WIDTH_CH2_V << AXI_DMA_RX_CRC_WIDTH_CH2_S)
#define AXI_DMA_RX_CRC_WIDTH_CH2_V 0x00000003U
#define AXI_DMA_RX_CRC_WIDTH_CH2_S 0
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S 2
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2 (BIT(2))
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH2_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH2_S)
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_V 0x00000001U
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_S 2
/** AXI_DMA_IN_CRC_CLEAR_CH2_REG register
* This register is used to clear ch2 crc result
@@ -3417,7 +3417,7 @@ extern "C" {
#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_S 0
/** AXI_DMA_TX_CRC_WIDTH_CH0_REG register
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -3429,13 +3429,13 @@ extern "C" {
#define AXI_DMA_TX_CRC_WIDTH_CH0_M (AXI_DMA_TX_CRC_WIDTH_CH0_V << AXI_DMA_TX_CRC_WIDTH_CH0_S)
#define AXI_DMA_TX_CRC_WIDTH_CH0_V 0x00000003U
#define AXI_DMA_TX_CRC_WIDTH_CH0_S 0
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S 2
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0 (BIT(2))
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH0_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH0_S)
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_V 0x00000001U
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_S 2
/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG register
* This register is used to clear ch0 crc result
@@ -4263,7 +4263,7 @@ extern "C" {
#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_S 0
/** AXI_DMA_TX_CRC_WIDTH_CH1_REG register
* This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
* This register is used to config tx ch1 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -4275,13 +4275,13 @@ extern "C" {
#define AXI_DMA_TX_CRC_WIDTH_CH1_M (AXI_DMA_TX_CRC_WIDTH_CH1_V << AXI_DMA_TX_CRC_WIDTH_CH1_S)
#define AXI_DMA_TX_CRC_WIDTH_CH1_V 0x00000003U
#define AXI_DMA_TX_CRC_WIDTH_CH1_S 0
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S 2
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1 (BIT(2))
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH1_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH1_S)
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_V 0x00000001U
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_S 2
/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG register
* This register is used to clear ch1 crc result
@@ -5109,7 +5109,7 @@ extern "C" {
#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_S 0
/** AXI_DMA_TX_CRC_WIDTH_CH2_REG register
* This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
* This register is used to config tx ch2 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -5121,13 +5121,13 @@ extern "C" {
#define AXI_DMA_TX_CRC_WIDTH_CH2_M (AXI_DMA_TX_CRC_WIDTH_CH2_V << AXI_DMA_TX_CRC_WIDTH_CH2_S)
#define AXI_DMA_TX_CRC_WIDTH_CH2_V 0x00000003U
#define AXI_DMA_TX_CRC_WIDTH_CH2_S 0
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S 2
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2 (BIT(2))
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH2_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH2_S)
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_V 0x00000001U
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_S 2
/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG register
* This register is used to clear ch2 crc result

12
components/soc/esp32p4/include/soc/axi_dma_struct.h
View File

@@ -604,7 +604,7 @@ typedef union {
} axi_dma_in_crc_init_data_chn_reg_t;
/** Type of rx_crc_width_chn register
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -614,10 +614,10 @@ typedef union {
* reserved
*/
uint32_t rx_crc_width_chn: 2;
/** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
/** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t rx_crc_lautch_flga_chn: 1;
uint32_t rx_crc_latch_flag_chn: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
@@ -1275,7 +1275,7 @@ typedef union {
} axi_dma_out_crc_init_data_chn_reg_t;
/** Type of tx_crc_width_chn register
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -1285,10 +1285,10 @@ typedef union {
* reserved
*/
uint32_t tx_crc_width_chn: 2;
/** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
/** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t tx_crc_lautch_flga_chn: 1;
uint32_t tx_crc_latch_flag_chn: 1;
uint32_t reserved_3: 29;
};
uint32_t val;

1
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -160,6 +160,7 @@
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_SUPPORT_CRC 1
#define SOC_GDMA_NUM_GROUPS_MAX 2
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_AXI_GDMA_SUPPORT_PSRAM 1