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feat(i2s): support i2s on esp32p4

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This commit is contained in:
laokaiyao
2023-06-16 15:15:23 +08:00
parent 492c819357
commit cf889f3c6d
21 changed files with 1568 additions and 372 deletions
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36
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -71,6 +71,10 @@ config SOC_I2C_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -433,7 +437,7 @@ config SOC_I2C_SUPPORT_RTC
config SOC_I2S_NUM
int
default 1
default 3
config SOC_I2S_HW_VERSION_2
bool
@@ -443,7 +447,7 @@ config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
config SOC_I2S_SUPPORTS_APLL
bool
default y
@@ -451,10 +455,38 @@ config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_PDM_MAX_RX_LINES
int
default 4
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y

15
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -150,6 +150,7 @@ typedef enum {
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
@@ -334,6 +335,20 @@ typedef enum {
///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**

184
components/soc/esp32p4/include/soc/i2s_struct.h
View File

@@ -277,6 +277,92 @@ typedef union {
uint32_t val;
} i2s_rx_pdm2pcm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
* I2S TX PDM bypass hp filter or not. The option has been removed.
*/
uint32_t tx_pdm_hp_bypass:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of rx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -371,7 +457,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@@ -384,7 +470,7 @@ typedef union {
uint32_t reserved_12:20;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@@ -530,89 +616,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -845,7 +848,7 @@ typedef union {
uint32_t val;
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
/** Type of conf_single_data register
* I2S signal data register
*/
typedef union {
@@ -856,7 +859,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -986,8 +989,8 @@ typedef struct {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
volatile i2s_fifo_cnt_reg_t fifo_cnt;
@@ -996,6 +999,9 @@ typedef struct {
volatile i2s_date_reg_t date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
extern i2s_dev_t I2S2;
#ifndef __cplusplus
_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");

19
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -50,6 +50,8 @@
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 //TODO: IDF-6508
#define SOC_RMT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
@@ -240,16 +242,19 @@
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
//TODO: IDF-6508
#define SOC_I2S_NUM (1U)
#define SOC_I2S_NUM (3U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (1)
#define SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER (1)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)