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refactor(rtc): move soc/rtc.h from soc to esp_hw_support component

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Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
This commit is contained in:
Song Ruo Jing
2024-01-03 15:28:29 +08:00
parent e81932d2b2
commit cf93777077
95 changed files with 494 additions and 644 deletions
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23
components/hal/esp32/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/dport_reg.h"
@@ -73,6 +72,10 @@ extern "C" {
#define CLK_LL_XTAL_32K_BOOTSTRAP_DRES_VAL 3
#define CLK_LL_XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
/* RC_FAST clock enable/disable wait time */
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
/* APLL multiplier output frequency range */
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define CLK_LL_APLL_MULTIPLIER_MIN_HZ (350000000) // 350 MHz
@@ -275,7 +278,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
}
/**
@@ -284,7 +287,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
}
/**
@@ -449,7 +452,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
if (pll_freq_mhz == CLK_LL_PLL_320M_FREQ_MHZ) {
/* Configure 320M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 32;
div10_8 = 0;
@@ -457,7 +460,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 6;
bw = 3;
break;
case RTC_XTAL_FREQ_26M:
case SOC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
@@ -465,7 +468,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 0;
bw = 1;
break;
case RTC_XTAL_FREQ_24M:
case SOC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 224;
div10_8 = 4;
@@ -487,7 +490,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
} else {
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 28;
div10_8 = 0;
@@ -495,7 +498,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 6;
bw = 3;
break;
case RTC_XTAL_FREQ_26M:
case SOC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 144;
div10_8 = 4;
@@ -503,7 +506,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 0;
bw = 1;
break;
case RTC_XTAL_FREQ_24M:
case SOC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 144;
div10_8 = 4;

9
components/hal/esp32/include/hal/rtc_cntl_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,7 +7,6 @@
#pragma once
#include "soc/soc.h"
#include "soc/rtc.h"
#include "esp_attr.h"
#include "clk_tree_ll.h"
#include "esp_rom_sys.h"
@@ -106,12 +105,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
return t;
}
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
{
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
}
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);