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refactor(rtc): move soc/rtc.h from soc to esp_hw_support component

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Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
This commit is contained in:
Song Ruo Jing
2024-01-03 15:28:29 +08:00
parent e81932d2b2
commit cf93777077
95 changed files with 494 additions and 644 deletions
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17
components/hal/esp32c2/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "soc/system_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h"
@@ -33,6 +32,10 @@ extern "C" {
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_40M_FREQ_MHZ
/* RC_FAST clock enable/disable wait time */
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
/**
* @brief XTAL32K_CLK enable modes
*/
@@ -65,7 +68,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
}
/**
@@ -74,7 +77,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
}
/**
@@ -238,7 +241,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_26M:
case SOC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 236;
dr1 = 4;
@@ -247,7 +250,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 0;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
div_ref = 0;
div7_0 = 11;
dr1 = 0;
@@ -256,7 +259,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
default:
div_ref = 0;
div7_0 = 8;

9
components/hal/esp32c2/include/hal/rtc_cntl_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,7 +7,6 @@
#pragma once
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
@@ -74,12 +73,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
return t;
}
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
{
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
}
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);