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refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in clk_tree_defs.h in soc component.
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -9,7 +9,6 @@
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/syscon_reg.h"
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@@ -35,7 +34,11 @@ extern "C" {
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#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
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// ESP32S2 only supports 40MHz crystal
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#define CLK_LL_XTAL_FREQ_MHZ (40)
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#define CLK_LL_XTAL_FREQ_MHZ (SOC_XTAL_FREQ_40M)
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/* RC_FAST clock enable/disable wait time */
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#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
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#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
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/* APLL configuration parameters */
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#define CLK_LL_APLL_SDM_STOP_VAL_1 0x09
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@@ -227,7 +230,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
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}
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/**
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@@ -236,7 +239,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
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}
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/**
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