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refactor(rtc): move soc/rtc.h from soc to esp_hw_support component

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Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
This commit is contained in:
Song Ruo Jing
2024-01-03 15:28:29 +08:00
parent e81932d2b2
commit cf93777077
95 changed files with 494 additions and 644 deletions
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25
components/hal/esp32s3/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "soc/system_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/regi2c_defs.h"
@@ -34,6 +33,10 @@ extern "C" {
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
/* RC_FAST clock enable/disable wait time */
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \
@@ -133,7 +136,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
}
/**
@@ -142,7 +145,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
}
/**
@@ -313,7 +316,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
@@ -322,7 +325,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 26;
dr1 = 1;
@@ -345,7 +348,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
} else {
/* Configure 320M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
@@ -354,7 +357,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 6;
dr1 = 0;
@@ -687,15 +690,15 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
* @brief Configure PLL frequency for MSPI timing tuning
* @note Only used by the MSPI Timing tuning driver
*
* @param xtal_freq Xtal frequency
* @param xtal_freq XTAL frequency
* @param pll_freq PLL frequency
* @param oc_div OC divider
* @param oc_ref_div OC ref divider
*/
static inline __attribute__((always_inline))
void clk_ll_bbpll_set_frequency_for_mspi_tuning(rtc_xtal_freq_t xtal_freq, int pll_freq, uint8_t oc_div, uint8_t oc_ref_div)
void clk_ll_bbpll_set_frequency_for_mspi_tuning(soc_xtal_freq_t xtal_freq, int pll_freq, uint8_t oc_div, uint8_t oc_ref_div)
{
HAL_ASSERT(xtal_freq == RTC_XTAL_FREQ_40M);
HAL_ASSERT(xtal_freq == SOC_XTAL_FREQ_40M);
uint32_t pll_reg = GET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
HAL_ASSERT(pll_reg == 0);

9
components/hal/esp32s3/include/hal/rtc_cntl_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,7 +7,6 @@
#pragma once
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
@@ -175,12 +174,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
return t;
}
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
{
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
}
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);