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refactor(xtensa): Rename specreg.h register macros

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This commit renames all registers in xtensa/specreg.h to by adding the
prefix XT_REG_. This is done to avoid naming collisions with similar
variable names. A new register file, viz., xt_specreg.h is created. The
previous names are still available to use but have been deprecated.

Closes https://github.com/espressif/esp-idf/issues/12723
Merges https://github.com/espressif/esp-idf/pull/16040
This commit is contained in:
Nebojsa Cvetkovic
2025-05-29 01:18:50 +01:00
committed by Sudeep Mohanty
parent 2f4c5d278e
commit d0ceef20f4
41 changed files with 824 additions and 289 deletions
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12
components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S
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@@ -24,9 +24,9 @@ esp_gdbstub_int:
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
rsr a0, XT_REG_PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
rsr a0, XT_REG_EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
@@ -35,21 +35,21 @@ esp_gdbstub_int:
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
rsr a0, XT_REG_EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
rsr a0, XT_REG_EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
/* Save context pointer as input parameter */
rsr a6, excsave1
rsr a3, EPS
rsr a3, XT_REG_EPS
s32i a3, sp, XT_STK_PS // store PS to the ps place
movi a3, gdbstub_handle_uart_int
callx0 a3

20
components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c
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@@ -7,7 +7,7 @@
#include <string.h>
#include "esp_gdbstub_common.h"
#include "soc/soc_memory_layout.h"
#include "xtensa/config/specreg.h"
#include "xtensa/config/xt_specreg.h"
#include "sdkconfig.h"
#include "esp_cpu.h"
#include "esp_ipc_isr.h"
@@ -35,8 +35,8 @@ static void update_regfile_common(esp_gdbstub_gdb_regfile_t *dst)
}
dst->windowbase = 0;
dst->windowstart = 0x1;
RSR(CONFIGID0, dst->configid0);
RSR(CONFIGID1, dst->configid1);
RSR(XT_REG_CONFIGID0, dst->configid0);
RSR(XT_REG_CONFIGID1, dst->configid1);
}
#if XCHAL_HAVE_FP
@@ -111,7 +111,7 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_
current_tcb_ptr = pxCurrentTCBs[esp_cpu_get_core_id()];
#endif
uint32_t cp_enabled;
RSR(CPENABLE, cp_enabled);
RSR(XT_REG_CPENABLE, cp_enabled);
// Check if the co-processor is enabled
if (cp_enabled) {
@@ -182,7 +182,7 @@ void esp_gdbstub_tcb_frame_to_regfile(dummy_tcb_t *tcb, esp_gdbstub_gdb_regfile_
#endif
uint32_t cp_enabled;
RSR(CPENABLE, cp_enabled);
RSR(XT_REG_CPENABLE, cp_enabled);
void *current_tcb_ptr = tcb;
uint32_t *current_fpu_ptr = NULL;
@@ -309,8 +309,8 @@ void esp_gdbstub_stall_other_cpus_end(void)
* */
void esp_gdbstub_clear_step(void)
{
WSR(ICOUNT, 0);
WSR(ICOUNTLEVEL, 0);
WSR(XT_REG_ICOUNT, 0);
WSR(XT_REG_ICOUNTLEVEL, 0);
}
/** @brief GDB do step
@@ -326,8 +326,8 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame)
level &= 0x7;
level += 1;
WSR(ICOUNTLEVEL, level);
WSR(ICOUNT, -2);
WSR(XT_REG_ICOUNTLEVEL, level);
WSR(XT_REG_ICOUNT, -2);
}
/** @brief GDB trigger other CPU
@@ -364,7 +364,7 @@ void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, ui
#if XCHAL_HAVE_FP
void *ptr1;
uint32_t cp_enabled;
RSR(CPENABLE, cp_enabled);
RSR(XT_REG_CPENABLE, cp_enabled);
if (cp_enabled != 0) {
if (reg_index == 87) {
asm volatile ("lsi f0, %0, 0" :: "a" (ptr0));

18
components/esp_gdbstub/src/port/xtensa/xt_debugexception.S
View File

@@ -22,9 +22,9 @@ _xt_panic_gdbstub:
s32i a0, sp, XT_STK_EXIT
s32i a0, sp, XT_STK_A0
rsr a0, PS /* save interruptee's PS */
rsr a0, XT_REG_PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
rsr a0, XT_REG_EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
call0 _xt_context_save /* Save full context*/
addi a7, sp, XT_STK_FRMSZ
@@ -33,29 +33,29 @@ _xt_panic_gdbstub:
s32i a13, sp, XT_STK_A13
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
rsr a0, XT_REG_EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
rsr a0, XT_REG_EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */
/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
wsr a0, PS
wsr a0, XT_REG_PS
//Call gdbstub handler
rsr a0,(EPC + XCHAL_DEBUGLEVEL)
rsr a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL)
s32i a0, sp, XT_STK_PC
mov a6, sp
rsr a9, EPS_6
rsr a9, XT_REG_EPS_6
s32i a9, sp, XT_STK_PS // store PS to the ps place
movi a11, gdbstub_handle_debug_int
callx4 a11 /* Call interrupt handler */
l32i a0, sp, XT_STK_PC
wsr a0,(EPC + XCHAL_DEBUGLEVEL)
wsr a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL)
call0 _xt_context_restore /* Restore full context*/
l32i a12, sp, XT_STK_A12
l32i a13, sp, XT_STK_A13