From d0e4d36fb6bca5719f025f9bb58bd223b69abd57 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 2 Feb 2023 14:46:44 +0800 Subject: [PATCH] esp_adc: support h2 oneshot mode and continuous mode --- .gitlab/ci/rules.yml | 26 + .gitlab/ci/target-test.yml | 16 + components/driver/deprecated/adc_legacy.c | 40 +- .../test_apps/legacy_adc_driver/README.md | 4 +- .../legacy_adc_driver/main/test_legacy_adc.c | 9 +- .../legacy_adc_driver/pytest_legacy_adc.py | 1 + components/esp_adc/CMakeLists.txt | 15 - .../esp32h2/include/adc_cali_schemes.h | 15 + components/esp_adc/test_apps/adc/README.md | 4 +- .../test_apps/adc/main/test_common_adc.h | 8 + .../esp_adc/test_apps/adc/pytest_adc.py | 1 + components/esp_hw_support/CMakeLists.txt | 1 - components/esp_hw_support/adc_share_hw_ctrl.c | 9 +- .../port/esp32c6/sar_periph_ctrl.c | 6 +- .../port/esp32h2/CMakeLists.txt | 3 +- .../port/esp32h2/sar_periph_ctrl.c | 108 +++ components/hal/CMakeLists.txt | 2 - components/hal/adc_hal_common.c | 2 + components/hal/adc_oneshot_hal.c | 3 - .../hal/esp32c6/include/hal/sar_ctrl_ll.h | 15 +- .../hal/esp32h2/include/hal/adc_hal_conf.h | 28 + components/hal/esp32h2/include/hal/adc_ll.h | 721 ++++++++++++++++++ .../hal/esp32h2/include/hal/sar_ctrl_ll.h | 72 ++ components/hal/include/hal/adc_types.h | 2 +- .../include/esp32c6/idf_performance_target.h | 13 +- .../include/esp32h2/idf_performance_target.h | 13 +- .../esp32c2/include/soc/Kconfig.soc_caps.in | 12 + components/soc/esp32c2/include/soc/soc_caps.h | 1 + .../esp32c3/include/soc/Kconfig.soc_caps.in | 8 + components/soc/esp32c3/include/soc/soc_caps.h | 1 + components/soc/esp32c6/include/soc/reg_base.h | 4 +- components/soc/esp32h2/adc_periph.c | 10 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 24 +- .../soc/esp32h2/include/soc/adc_channel.h | 23 +- .../soc/esp32h2/include/soc/clk_tree_defs.h | 5 +- components/soc/esp32h2/include/soc/reg_base.h | 2 + .../soc/esp32h2/include/soc/regi2c_saradc.h | 8 + components/soc/esp32h2/include/soc/soc_caps.h | 10 +- .../esp32s2/include/soc/Kconfig.soc_caps.in | 8 + components/soc/esp32s2/include/soc/soc_caps.h | 1 + .../esp32s3/include/soc/Kconfig.soc_caps.in | 8 + components/soc/esp32s3/include/soc/soc_caps.h | 1 + docs/docs_not_updated/esp32h2.txt | 2 - .../peripherals/adc/continuous_read/README.md | 4 +- .../continuous_read/pytest_adc_continuous.py | 1 + .../peripherals/adc/oneshot_read/README.md | 4 +- .../adc/oneshot_read/pytest_adc_oneshot.py | 1 + 47 files changed, 1176 insertions(+), 99 deletions(-) create mode 100644 components/esp_adc/esp32h2/include/adc_cali_schemes.h create mode 100644 components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c create mode 100644 components/hal/esp32h2/include/hal/adc_hal_conf.h create mode 100644 components/hal/esp32h2/include/hal/adc_ll.h create mode 100644 components/hal/esp32h2/include/hal/sar_ctrl_ll.h diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml index f2fbf384f5..c5c15d13f2 100644 --- a/.gitlab/ci/rules.yml +++ b/.gitlab/ci/rules.yml @@ -2100,6 +2100,19 @@ - <<: *if-dev-push changes: *patterns-component_ut +.rules:test:component_ut-esp32h2-adc: + rules: + - <<: *if-revert-branch + when: never + - <<: *if-protected + - <<: *if-label-build-only + when: never + - <<: *if-label-component_ut + - <<: *if-label-component_ut_esp32h2 + - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-target_test-adc + .rules:test:component_ut-esp32h4-i154: rules: - <<: *if-revert-branch @@ -2567,6 +2580,19 @@ - <<: *if-dev-push changes: *patterns-example_test +.rules:test:example_test-esp32h2-adc: + rules: + - <<: *if-revert-branch + when: never + - <<: *if-protected + - <<: *if-label-build-only + when: never + - <<: *if-label-example_test + - <<: *if-label-example_test_esp32h2 + - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-target_test-adc + .rules:test:example_test-esp32s2: rules: - <<: *if-revert-branch diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index 7713d67f04..c6a82f61be 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -480,6 +480,14 @@ example_test_pytest_esp32c6_adc: - build_pytest_examples_esp32c6 tags: [ esp32c6, adc ] +example_test_pytest_esp32h2_adc: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32h2-adc + needs: + - build_pytest_examples_esp32h2 + tags: [ esp32h2, adc ] + .pytest_components_dir_template: extends: .pytest_template variables: @@ -836,6 +844,14 @@ component_ut_pytest_esp32h2_generic: tags: [ esp32h2, generic ] parallel: 2 +component_ut_pytest_esp32h2_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32h2-adc + needs: + - build_pytest_components_esp32h2 + tags: [ esp32h2, adc ] + component_ut_pytest_esp32c6_generic_multi_device: extends: - .pytest_components_dir_template diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index 79edbbe503..8232973304 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -101,7 +101,9 @@ static esp_pm_lock_handle_t s_adc2_arbiter_lock; #endif //CONFIG_PM_ENABLE #endif // !CONFIG_IDF_TARGET_ESP32 -static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw); +static uint32_t clk_src_freq_hz; + +static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src_freq_hz, int *out_raw); /*--------------------------------------------------------------- ADC Common @@ -276,6 +278,13 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); ESP_RETURN_ON_FALSE(atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err"); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + if (!clk_src_freq_hz) { + esp_err_t ret = clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + assert(ret == ESP_OK); + } +#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + adc_common_gpio_init(ADC_UNIT_1, channel); SARADC1_ENTER(); adc_rtc_chan_init(ADC_UNIT_1); @@ -387,7 +396,7 @@ int adc1_get_raw(adc1_channel_t channel) #endif adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC); //Set controller adc_oneshot_ll_set_channel(ADC_UNIT_1, channel); - adc_hal_convert(ADC_UNIT_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid. + adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &adc_value); //Start conversion, For ADC1, the data always valid. #if !CONFIG_IDF_TARGET_ESP32 adc_ll_rtc_reset(); //Reset FSM of rtc controller #endif @@ -428,6 +437,12 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) { ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); ESP_RETURN_ON_FALSE(atten <= SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err"); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + if (!clk_src_freq_hz) { + esp_err_t ret = clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz); + assert(ret == ESP_OK); + } +#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED adc_common_gpio_init(ADC_UNIT_2, channel); @@ -572,7 +587,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * #endif //CONFIG_IDF_TARGET_ESP32 adc_oneshot_ll_set_channel(ADC_UNIT_2, channel); - ret = adc_hal_convert(ADC_UNIT_2, channel, &adc_value); + ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, &adc_value); if (ret != ESP_OK) { adc_value = -1; } @@ -766,7 +781,7 @@ int adc1_get_raw(adc1_channel_t channel) ADC_REG_LOCK_ENTER(); adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten); - adc_hal_convert(ADC_UNIT_1, channel, &raw_out); + adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out); ADC_REG_LOCK_EXIT(); sar_periph_ctrl_adc_oneshot_power_release(); @@ -820,7 +835,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * ADC_REG_LOCK_ENTER(); adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten); - ret = adc_hal_convert(ADC_UNIT_2, channel, raw_out); + ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, raw_out); ADC_REG_LOCK_EXIT(); sar_periph_ctrl_adc_oneshot_power_release(); @@ -833,7 +848,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED -static void adc_hal_onetime_start(adc_unit_t adc_n) +static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz) { #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED (void)adc_n; @@ -841,16 +856,13 @@ static void adc_hal_onetime_start(adc_unit_t adc_n) * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller * clock cycle. - * - * This limitation will be removed in hardware future versions. - * */ - uint32_t digi_clk = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1); + uint32_t digi_clk = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1); //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough. uint32_t delay = (1000 * 1000) / digi_clk + 1; //3 ADC digital controller clock cycle delay = delay * 3; - //This coefficient (8) is got from test. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed. + //This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed. if (digi_clk >= APB_CLK_FREQ/8) { delay = 0; } @@ -861,19 +873,21 @@ static void adc_hal_onetime_start(adc_unit_t adc_n) //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr. #else + (void)clk_src_freq_hz; adc_oneshot_ll_start(adc_n); #endif } -static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw) +static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src_freq_hz, int *out_raw) { + uint32_t event = (adc_n == ADC_UNIT_1) ? ADC_LL_EVENT_ADC1_ONESHOT_DONE : ADC_LL_EVENT_ADC2_ONESHOT_DONE; adc_oneshot_ll_clear_event(event); adc_oneshot_ll_disable_all_unit(); adc_oneshot_ll_enable(adc_n); adc_oneshot_ll_set_channel(adc_n, channel); - adc_hal_onetime_start(adc_n); + adc_hal_onetime_start(adc_n, clk_src_freq_hz); while (adc_oneshot_ll_get_event(event) != true) { ; diff --git a/components/driver/test_apps/legacy_adc_driver/README.md b/components/driver/test_apps/legacy_adc_driver/README.md index 7e7523ec85..a8b7833fa3 100644 --- a/components/driver/test_apps/legacy_adc_driver/README.md +++ b/components/driver/test_apps/legacy_adc_driver/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c index a5b58e9720..f68991fdab 100644 --- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c +++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -60,6 +60,13 @@ #define ADC_TEST_HIGH_VAL 4081 #define ADC_TEST_HIGH_THRESH 200 +#elif CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6216 +#define ADC_TEST_LOW_VAL 2144 +#define ADC_TEST_LOW_THRESH 200 + +#define ADC_TEST_HIGH_VAL 4081 +#define ADC_TEST_HIGH_THRESH 200 + #endif //ADC Channels diff --git a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py index 081f0d547e..09667bc95b 100644 --- a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py +++ b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py @@ -10,6 +10,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s3 @pytest.mark.esp32c3 @pytest.mark.esp32c6 +@pytest.mark.esp32h2 @pytest.mark.adc @pytest.mark.parametrize( 'config', diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt index 2f53681010..5c8c3ed1a3 100644 --- a/components/esp_adc/CMakeLists.txt +++ b/components/esp_adc/CMakeLists.txt @@ -1,8 +1,3 @@ -if(IDF_TARGET STREQUAL "esp32h2") - # TODO : IDF-6214 - return() -endif() - idf_build_get_property(target IDF_TARGET) set(includes "include" "interface" "${target}/include" "deprecated/include") @@ -36,16 +31,6 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c") endif() -# ESP32H2-TODO -if(CONFIG_IDF_TARGET_ESP32H2) - # TODO: IDF-6214 - list(REMOVE_ITEM srcs - "adc_cali_curve_fitting.c" - "adc_oneshot.c" - "adc_common.c" - ) -endif() - idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_REQUIRES driver efuse diff --git a/components/esp_adc/esp32h2/include/adc_cali_schemes.h b/components/esp_adc/esp32h2/include/adc_cali_schemes.h new file mode 100644 index 0000000000..16dc6be4f1 --- /dev/null +++ b/components/esp_adc/esp32h2/include/adc_cali_schemes.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file adc_cali_schemes.h + * + * @brief Supported calibration schemes + */ + +//Now no scheme supported diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md index 7e7523ec85..a8b7833fa3 100644 --- a/components/esp_adc/test_apps/adc/README.md +++ b/components/esp_adc/test_apps/adc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h index d443d33235..87f81d024e 100644 --- a/components/esp_adc/test_apps/adc/main/test_common_adc.h +++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h @@ -75,6 +75,14 @@ extern "C" { #define ADC_TEST_LOW_VAL 2144 #define ADC_TEST_LOW_THRESH 200 +#define ADC_TEST_HIGH_VAL 4081 +#define ADC_TEST_HIGH_VAL_DMA 4081 +#define ADC_TEST_HIGH_THRESH 200 + +#elif CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6216 +#define ADC_TEST_LOW_VAL 2144 +#define ADC_TEST_LOW_THRESH 200 + #define ADC_TEST_HIGH_VAL 4081 #define ADC_TEST_HIGH_VAL_DMA 4081 #define ADC_TEST_HIGH_THRESH 200 diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index 31ce345c8d..65be906b32 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -10,6 +10,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s3 @pytest.mark.esp32c3 @pytest.mark.esp32c6 +@pytest.mark.esp32h2 @pytest.mark.adc @pytest.mark.parametrize('config', [ 'iram_safe', diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index f20e393137..4d9f39c0cf 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -104,7 +104,6 @@ if(NOT BOOTLOADER_BUILD) if(CONFIG_IDF_TARGET_ESP32H2) list(REMOVE_ITEM srcs - "adc_share_hw_ctrl.c" # TODO: IDF-6215 "sleep_cpu.c" # TODO: IDF-6267 "sleep_modes.c" # TODO: IDF-6267 ) diff --git a/components/esp_hw_support/adc_share_hw_ctrl.c b/components/esp_hw_support/adc_share_hw_ctrl.c index 64e66e9f7e..fa1bb32a38 100644 --- a/components/esp_hw_support/adc_share_hw_ctrl.c +++ b/components/esp_hw_support/adc_share_hw_ctrl.c @@ -71,7 +71,9 @@ void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten) if (version == ESP_EFUSE_ADC_CALIB_VER) { init_code = esp_efuse_rtc_calib_get_init_code(version, adc_n, atten); - } else { + } +#if SOC_ADC_SELF_HW_CALI_SUPPORTED + else { ESP_EARLY_LOGD(TAG, "Calibration eFuse is not configured, use self-calibration for ICode"); sar_periph_ctrl_adc_oneshot_power_acquire(); portENTER_CRITICAL(&rtc_spinlock); @@ -81,6 +83,11 @@ void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten) portEXIT_CRITICAL(&rtc_spinlock); sar_periph_ctrl_adc_oneshot_power_release(); } +#else + else { + ESP_EARLY_LOGD(TAG, "ICode self-calibration isn't supported"); + } +#endif //SOC_ADC_SELF_HW_CALI_SUPPORTED s_adc_cali_param[adc_n][atten] = init_code; ESP_EARLY_LOGV(TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n + 1, atten, init_code); diff --git a/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c index 58a65fca09..01b463ccc0 100644 --- a/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c @@ -28,12 +28,14 @@ void sar_periph_ctrl_init(void) { sar_ctrl_ll_force_power_ctrl_from_pwdet(true); - //TODO: IDF-6124 + //Add other periph power control initialisation here } void sar_periph_ctrl_power_disable(void) { - //TODO: IDF-6124 + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(false); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); } /** diff --git a/components/esp_hw_support/port/esp32h2/CMakeLists.txt b/components/esp_hw_support/port/esp32h2/CMakeLists.txt index 596ac63305..9c1949a12c 100644 --- a/components/esp_hw_support/port/esp32h2/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32h2/CMakeLists.txt @@ -8,7 +8,8 @@ set(srcs "rtc_clk_init.c" ) if(NOT BOOTLOADER_BUILD) - list(APPEND srcs "esp_crypto_lock.c") + list(APPEND srcs "sar_periph_ctrl.c" + "esp_crypto_lock.c") endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") diff --git a/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c new file mode 100644 index 0000000000..fce3cc7561 --- /dev/null +++ b/components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * SAR related peripherals are interdependent. This file + * provides a united control to these registers, as multiple + * components require these controls. + * + * Related peripherals are: + * - ADC + * - PWDET + */ + +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "esp_private/sar_periph_ctrl.h" +#include "hal/sar_ctrl_ll.h" + +static const char *TAG = "sar_periph_ctrl"; +extern portMUX_TYPE rtc_spinlock; + + +void sar_periph_ctrl_init(void) +{ + sar_ctrl_ll_force_power_ctrl_from_pwdet(true); + + //Add other periph power control initialisation here +} + +void sar_periph_ctrl_power_disable(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(false); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + +/** + * This gets incremented when s_sar_power_acquire() is called, + * and decremented when s_sar_power_release() is called. + * PWDET is powered down when the value reaches zero. + * Should be modified within critical section. + */ +static int s_pwdet_power_on_cnt; + +static void s_sar_power_acquire(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + s_pwdet_power_on_cnt++; + if (s_pwdet_power_on_cnt == 1) { + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); + } + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + +static void s_sar_power_release(void) +{ + portENTER_CRITICAL_SAFE(&rtc_spinlock); + s_pwdet_power_on_cnt--; + if (s_pwdet_power_on_cnt < 0) { + portEXIT_CRITICAL(&rtc_spinlock); + ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); + abort(); + } else if (s_pwdet_power_on_cnt == 0) { + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); + } + portEXIT_CRITICAL_SAFE(&rtc_spinlock); +} + + +/*------------------------------------------------------------------------------ +* PWDET Power +*----------------------------------------------------------------------------*/ +void sar_periph_ctrl_pwdet_power_acquire(void) +{ + s_sar_power_acquire(); +} + +void sar_periph_ctrl_pwdet_power_release(void) +{ + s_sar_power_release(); +} + + +/*------------------------------------------------------------------------------ +* ADC Power +*----------------------------------------------------------------------------*/ +void sar_periph_ctrl_adc_oneshot_power_acquire(void) +{ + s_sar_power_acquire(); +} + +void sar_periph_ctrl_adc_oneshot_power_release(void) +{ + s_sar_power_release(); +} + +void sar_periph_ctrl_adc_continuous_power_acquire(void) +{ + s_sar_power_acquire(); +} + +void sar_periph_ctrl_adc_continuous_power_release(void) +{ + s_sar_power_release(); +} diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 1515a06d4b..6582e5108a 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -236,8 +236,6 @@ if(NOT BOOTLOADER_BUILD) ) list(REMOVE_ITEM srcs - "adc_oneshot_hal.c" # TODO: IDF-6214 - "adc_hal_common.c" # TODO: IDF-6215 "esp32h2/rtc_cntl_hal.c" "esp32h2/pmu_hal.c" # TODO: IDF-6267 ) diff --git a/components/hal/adc_hal_common.c b/components/hal/adc_hal_common.c index 8aeb1e379c..ee530e6a7e 100644 --- a/components/hal/adc_hal_common.c +++ b/components/hal/adc_hal_common.c @@ -104,6 +104,7 @@ void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param) } } +#if SOC_ADC_SELF_HW_CALI_SUPPORTED static void cal_setup(adc_unit_t adc_n, adc_atten_t atten) { adc_hal_set_controller(adc_n, ADC_HAL_SINGLE_READ_MODE); @@ -205,4 +206,5 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte return ret; return 0; } +#endif //#if SOC_ADC_SELF_HW_CALI_SUPPORTED #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED diff --git a/components/hal/adc_oneshot_hal.c b/components/hal/adc_oneshot_hal.c index 3b1c7f3bfa..720779823b 100644 --- a/components/hal/adc_oneshot_hal.c +++ b/components/hal/adc_oneshot_hal.c @@ -85,9 +85,6 @@ static void adc_hal_onetime_start(adc_unit_t unit) * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller * clock cycle. - * - * This limitation will be removed in hardware future versions. - * */ uint32_t digi_clk = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1); //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough. diff --git a/components/hal/esp32c6/include/hal/sar_ctrl_ll.h b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h index 1fda4e77de..a4dc35140e 100644 --- a/components/hal/esp32c6/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h @@ -26,9 +26,8 @@ extern "C" { #endif -#define PWDET_CONF_REG 0x600A8010 -#define PWDET_SAR_POWER_FORCE BIT(24) -#define PWDET_SAR_POWER_CNTL BIT(23) +#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) +#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) typedef enum { @@ -48,13 +47,13 @@ typedef enum { static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode) { if (mode == SAR_CTRL_LL_POWER_FSM) { - REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); } else if (mode == SAR_CTRL_LL_POWER_ON) { - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); } else if (mode == SAR_CTRL_LL_POWER_OFF) { - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); - REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); } } diff --git a/components/hal/esp32h2/include/hal/adc_hal_conf.h b/components/hal/esp32h2/include/hal/adc_hal_conf.h new file mode 100644 index 0000000000..28bb7400e3 --- /dev/null +++ b/components/hal/esp32h2/include/hal/adc_hal_conf.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/*--------------------------------------------------------------- + Single Read +---------------------------------------------------------------*/ +#define ADC_HAL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_HAL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2) + +/*--------------------------------------------------------------- + DMA Read +---------------------------------------------------------------*/ +#define ADC_HAL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) +#define ADC_HAL_FSM_RSTB_WAIT_DEFAULT (8) +#define ADC_HAL_FSM_START_WAIT_DEFAULT (5) +#define ADC_HAL_FSM_STANDBY_WAIT_DEFAULT (100) +#define ADC_HAL_SAMPLE_CYCLE_DEFAULT (2) +#define ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT (2) + +/*--------------------------------------------------------------- + PWDET (Power Detect) +---------------------------------------------------------------*/ +#define ADC_HAL_PWDET_CCT_DEFAULT (4) diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h new file mode 100644 index 0000000000..2994569887 --- /dev/null +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -0,0 +1,721 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "esp_attr.h" + +#include "soc/adc_periph.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/pmu_reg.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/misc.h" +#include "hal/assert.h" +#include "hal/adc_types.h" +#include "hal/adc_types_private.h" +#include "hal/regi2c_ctrl.h" +#include "hal/sar_ctrl_ll.h" + +#include "soc/regi2c_saradc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 +#define ADC_LL_CLKM_DIV_B_DEFAULT 1 +#define ADC_LL_CLKM_DIV_A_DEFAULT 0 +#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 +#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 + +#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) +#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) +#define ADC_LL_EVENT_THRES0_HIGH BIT(29) +#define ADC_LL_EVENT_THRES1_HIGH BIT(28) +#define ADC_LL_EVENT_THRES0_LOW BIT(27) +#define ADC_LL_EVENT_THRES1_LOW BIT(26) + +typedef enum { + ADC_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ + ADC_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ + ADC_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */ + ADC_POWER_MAX, /*!< For parameter check. */ +} adc_ll_power_t; + +typedef enum { + ADC_LL_CTRL_DIG = 0, ///< ADC digital controller +} adc_ll_controller_t; + +/** + * @brief ADC digital controller (DMA mode) work mode. + * + * @note The conversion mode affects the sampling frequency: + * ESP32H2 only support ONLY_ADC1 mode + * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. + */ +typedef enum { + ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion +} adc_ll_digi_convert_mode_t; + +typedef struct { + union { + struct { + uint8_t atten: 2; + uint8_t channel: 3; + uint8_t unit: 1; + uint8_t reserved: 2; + }; + uint8_t val; + }; +} __attribute__((packed)) adc_ll_digi_pattern_table_t; + +/*--------------------------------------------------------------- + Digital controller setting +---------------------------------------------------------------*/ + +/** + * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms. + * + * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor. + * @param start_wait Delay time after open xpd. + * @param standby_wait Delay time to close xpd. + */ +static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) +{ + // Internal FSM reset wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_rstb_wait, rst_wait); + // Internal FSM start wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_xpd_wait, start_wait); + // Internal FSM standby wait time + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_standby_wait, standby_wait); +} + +/** + * Set adc sample cycle for digital controller. + * + * @note Normally, please use default value. + * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor. + * Range: 2 ~ 0xFF. + */ +static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) +{ + /* Peripheral reg i2c has powered up in rtc_init, write directly */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); +} + +/** + * Set SAR ADC module clock division factor. + * SAR ADC clock divided from digital controller clock. + * + * @param div Division factor. + */ +static inline void adc_ll_digi_set_clk_div(uint32_t div) +{ + /* ADC clock divided from digital controller clock clk */ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div); +} + +/** + * Set adc max conversion number for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param meas_num Max conversion number. Range: 0 ~ 255. + */ +static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl2, saradc_saradc_max_meas_num, meas_num); +} + +/** + * Enable max conversion number detection for digital controller. + * If the number of ADC conversion is equal to the maximum, the conversion is stopped. + * + * @param enable true: enable; false: disable + */ +static inline void adc_ll_digi_convert_limit_enable(bool enable) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_meas_num_limit = enable; +} + +/** + * Set adc conversion mode for digital controller. + * + * @note ESP32H2 only support ADC1 single mode. + * + * @param mode Conversion mode select. + */ +static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) +{ + //ESP32H2 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode +} + +/** + * Set pattern table length for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param patt_len Items range: 1 ~ 8. + */ +static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1; +} + +/** + * Set pattern table for digital controller. + * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection, + * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the + * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. + * + * @param adc_n ADC unit. + * @param pattern_index Items index. Range: 0 ~ 7. + * @param pattern Stored conversion rules. + */ +static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) +{ + uint32_t tab; + uint8_t index = pattern_index / 4; + uint8_t offset = (pattern_index % 4) * 6; + adc_ll_digi_pattern_table_t pattern = {0}; + + pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); + if (index == 0) { + tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back + } else { + tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data + APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back + } +} + +/** + * Reset the pattern table pointer, then take the measurement rule from table header in next measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_p_clear = 0; +} + +/** + * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. + * + * @note Only ADC2 have arbiter function. + * @param cycle range: 0 ~ 4. + */ +static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_wait_arb_cycle = cycle; +} + +/** + * ADC Digital controller output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en) +{ + if (adc_n == ADC_UNIT_1) { + APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert + } +} + +/** + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. + * + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. + */ +static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle; +} + +/** + * Enable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_enable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1; +} + +/** + * Disable digital controller timer to trigger the measurement. + */ +static inline void adc_ll_digi_trigger_disable(void) +{ + APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0; +} + +/** + * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. + * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1). + * + * @param div_num Division factor. Range: 0 ~ 255. + * @param div_b Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. + */ +static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num); + PCR.saradc_clkm_conf.saradc_clkm_div_b = div_b; + PCR.saradc_clkm_conf.saradc_clkm_div_a = div_a; +} + +/** + * Enable clock and select clock source for ADC digital controller. + * + * @param clk_src clock source for ADC digital controller. + */ +static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) +{ + switch (clk_src) { + case ADC_DIGI_CLK_SRC_XTAL: + PCR.saradc_clkm_conf.saradc_clkm_sel = 0; + break; + case ADC_DIGI_CLK_SRC_PLL_F96M: + PCR.saradc_clkm_conf.saradc_clkm_sel = 1; + break; + case ADC_DIGI_CLK_SRC_RC_FAST: + PCR.saradc_clkm_conf.saradc_clkm_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock"); + } + // Enable ADC_CTRL_CLK (i.e. digital domain clock) + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; +} + +/** + * Disable clock for ADC digital controller. + */ +static inline void adc_ll_digi_controller_clk_disable(void) +{ + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; +} + +/** + * Reset adc digital controller filter. + * + * @param idx Filter index + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n) +{ + (void)adc_n; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 1; + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_reset = 0; +} + +/** + * Set adc digital controller filter coeff. + * + * @param idx filter index + * @param adc_n adc unit + * @param channel adc channel + * @param coeff filter coeff + */ +static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff) +{ + uint32_t factor_reg_val = 0; + switch (coeff) { + case ADC_DIGI_IIR_FILTER_COEFF_2: + factor_reg_val = 1; + break; + case ADC_DIGI_IIR_FILTER_COEFF_4: + factor_reg_val = 2; + break; + case ADC_DIGI_IIR_FILTER_COEFF_8: + factor_reg_val = 3; + break; + case ADC_DIGI_IIR_FILTER_COEFF_16: + factor_reg_val = 4; + break; + case ADC_DIGI_IIR_FILTER_COEFF_64: + factor_reg_val = 6; + break; + default: + HAL_ASSERT(false); + } + + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = factor_reg_val; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7); + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = factor_reg_val; + } +} + +/** + * Enable adc digital controller filter. + * Filtering the ADC data to obtain smooth data at higher sampling rates. + * + * @param idx filter index + * @param adc_n ADC unit + * @param enable Enable / Disable + */ +static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable) +{ + (void)adc_n; + if (!enable) { + if (idx == ADC_DIGI_IIR_FILTER_0) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel0 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor0 = 0; + } else if (idx == ADC_DIGI_IIR_FILTER_1) { + APB_SARADC.saradc_filter_ctrl0.saradc_apb_saradc_filter_channel1 = 0xF; + APB_SARADC.saradc_filter_ctrl1.saradc_apb_saradc_filter_factor1 = 0; + } + } + //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled. +} + +/** + * Set monitor mode of adc digital controller. + * + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param adc_n ADC unit. + * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. + * false: If ADC_OUT < threshold, Generates monitor interrupt. + */ +static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg) +{ + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_high = cfg->h_threshold; + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_low = cfg->l_threshold; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_low = cfg->h_threshold; + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_low = cfg->l_threshold; + } +} + +/** + * Enable/disable monitor of adc digital controller. + * + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param adc_n ADC unit. + */ +static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) +{ + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.saradc_thres0_ctrl.saradc_apb_saradc_thres0_channel = 0xF; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.saradc_thres1_ctrl.saradc_apb_saradc_thres1_channel = 0xF; + } +} + +/** + * Set DMA eof num of adc digital controller. + * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. + * + * @param num eof num of DMA. + */ +static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_dma_conf, saradc_apb_adc_eof_num, num); +} + +/** + * Enable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_enable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 1; +} + +/** + * Disable output data to DMA from adc digital controller. + */ +static inline void adc_ll_digi_dma_disable(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_trans = 0; +} + +/** + * Reset adc digital controller. + */ +static inline void adc_ll_digi_reset(void) +{ + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1; + APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0; +} + +/*--------------------------------------------------------------- + PWDET(Power detect) controller setting +---------------------------------------------------------------*/ +/** + * Set adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @param cct Range: 0 ~ 7. + */ +static inline void adc_ll_pwdet_set_cct(uint32_t cct) +{ + (void)cct; +} + +/** + * Get adc cct for PWDET controller. + * + * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. + * @return cct Range: 0 ~ 7. + */ +static inline uint32_t adc_ll_pwdet_get_cct(void) +{ + return 0; +} + +/*--------------------------------------------------------------- + Common setting +---------------------------------------------------------------*/ +/** + * Set ADC module power management. + * + * @param manage Set ADC power status. + */ +static inline void adc_ll_set_power_manage(adc_ll_power_t manage) +{ + /* Bit1 0:Fsm 1: SW mode + Bit0 0:SW mode power down 1: SW mode power on */ + if (manage == ADC_POWER_SW_ON) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3; + } else if (manage == ADC_POWER_BY_FSM) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0; + } else if (manage == ADC_POWER_SW_OFF) { + APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0; + APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2; + } +} + +__attribute__((always_inline)) +static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl) +{ + //Not used on ESP32H2 +} + +/* ADC calibration code. */ +/** + * @brief Set common calibration configuration. Should be shared with other parts (PWDET). + */ +__attribute__((always_inline)) +static inline void adc_ll_calibration_init(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); +} + +/** + * Set the calibration result to ADC. + * + * @note Different ADC units and different attenuation options use different calibration data (initial data). + * + * @param adc_n ADC index number. + */ +__attribute__((always_inline)) +static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + uint8_t msb = param >> 8; + uint8_t lsb = param & 0xFF; + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); +} + +/*--------------------------------------------------------------- + Oneshot Read +---------------------------------------------------------------*/ +/** + * Set adc output data format for oneshot mode + * + * @note ESP32H2 Oneshot mode only supports 12bit. + * @param adc_n ADC unit. + * @param bits Output data bits width option. + */ +static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits) +{ + //ESP32H2 only supports 12bit, leave here for compatibility + HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); +} + +/** + * Enable adc channel to start convert. + * + * @note Only one channel can be selected for measurement. + * + * @param adc_n ADC unit. + * @param channel ADC channel number for each ADCn. + */ +static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel); +} + +/** + * Disable adc channel to start convert. + * + * @note Only one channel can be selected in once measurement. + * + * @param adc_n ADC unit. + */ +static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF); +} + +/** + * Start oneshot conversion by software + * + * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle, + * otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow. + * This hardware limitation will be removed in future versions. + */ +static inline void adc_oneshot_ll_start(bool val) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = val; +} + +/** + * Clear the event for each ADCn for Oneshot mode + * + * @param event ADC event + */ +static inline void adc_oneshot_ll_clear_event(uint32_t event_mask) +{ + APB_SARADC.saradc_int_clr.val |= event_mask; +} + +/** + * Check the event for each ADCn for Oneshot mode + * + * @param event ADC event + * + * @return + * -true : The conversion process is finish. + * -false : The conversion process is not finish. + */ +static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) +{ + return (APB_SARADC.saradc_int_raw.val & event_mask); +} + +/** + * Get the converted value for each ADCn for controller. + * + * @param adc_n ADC unit. + * @return + * - Converted value. + */ +static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + uint32_t ret_val = 0; + ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; + return ret_val; +} + +/** + * Analyze whether the obtained raw data is correct. + * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. + * + * @param adc_n ADC unit. + * @param raw_data ADC raw data input (convert value). + * @return + * - 1: The data is correct to use. + * - 0: The data is invalid. + */ +static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + return true; +} + +/** + * ADC module RTC output data invert or not. + * + * @param adc_n ADC unit. + * @param inv_en data invert or not. + */ +static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)inv_en; + //For compatibility +} + +/** + * Enable oneshot conversion trigger + * + * @param adc_n ADC unit + */ +static inline void adc_oneshot_ll_enable(adc_unit_t adc_n) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1; +} + +/** + * Disable oneshot conversion trigger for all the ADC units + */ +static inline void adc_oneshot_ll_disable_all_unit(void) +{ + APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0; + APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0; +} + +/** + * Set attenuation + * + * @note Attenuation is for all channels + * + * @param adc_n ADC unit + * @param channel ADC channel + * @param atten ADC attenuation + */ +static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + // Attenuation is for all channels, unit and channel are for compatibility + APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten; +} + +/** + * Get the attenuation of a particular channel on ADCn. + * + * @param adc_n ADC unit. + * @param channel ADCn channel number. + * @return atten The attenuation option. + */ +__attribute__((always_inline)) +static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel) +{ + HAL_ASSERT(adc_n == ADC_UNIT_1); + (void)channel; + return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/sar_ctrl_ll.h b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h new file mode 100644 index 0000000000..a4dc35140e --- /dev/null +++ b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * SAR related peripherals are interdependent. + * Related peripherals are: + * - ADC + * - PWDET + * + * All of above peripherals require SAR to work correctly. + * As SAR has some registers that will influence above mentioned peripherals. + * This file gives an abstraction for such registers + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/apb_saradc_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) +#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) + + +typedef enum { + SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM + SAR_CTRL_LL_POWER_ON, //SAR power on + SAR_CTRL_LL_POWER_OFF, //SAR power off +} sar_ctrl_ll_power_t; + +/*--------------------------------------------------------------- + SAR power control +---------------------------------------------------------------*/ +/** + * @brief Set SAR power mode when controlled by PWDET + * + * @param[in] mode See `sar_ctrl_ll_power_t` + */ +static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode) +{ + if (mode == SAR_CTRL_LL_POWER_FSM) { + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + } else if (mode == SAR_CTRL_LL_POWER_ON) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } else if (mode == SAR_CTRL_LL_POWER_OFF) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } +} + +/** + * @brief Set SAR power ctrl source + * + * @param[in] force set PWDET as SAR power ctrl source when force is true + */ +static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force) +{ + APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index b8cc83b245..53b501889c 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -184,7 +184,7 @@ typedef struct { }; } adc_digi_output_data_t; -#elif CONFIG_IDF_TARGET_ESP32C6 +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 /** * @brief ADC digital controller (DMA mode) output data format. * Used to analyze the acquired ADC (DMA) data. diff --git a/components/idf_test/include/esp32c6/idf_performance_target.h b/components/idf_test/include/esp32c6/idf_performance_target.h index 7cb944229f..59a2c554fc 100644 --- a/components/idf_test/include/esp32c6/idf_performance_target.h +++ b/components/idf_test/include/esp32c6/idf_performance_target.h @@ -22,9 +22,10 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 8 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 7 +//TODO: IDF-5312 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 10 diff --git a/components/idf_test/include/esp32h2/idf_performance_target.h b/components/idf_test/include/esp32h2/idf_performance_target.h index fb78fdb829..9e03c51634 100644 --- a/components/idf_test/include/esp32h2/idf_performance_target.h +++ b/components/idf_test/include/esp32h2/idf_performance_target.h @@ -27,9 +27,10 @@ #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 8 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 7 -#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 7 +//TODO: IDF-6216 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16 10 +#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64 10 diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index dcab59db53..d4dec8c597 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -163,6 +163,18 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED bool default y +config SOC_ADC_SELF_HW_CALI_SUPPORTED + bool + default y + +config SOC_ADC_DIG_CLK_XTAL_SUPPORTED + bool + default y + +config SOC_ADC_DIG_CLK_PLL_F80M_SUPPORTED + bool + default y + config SOC_BROWNOUT_RESET_SUPPORTED bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 9b6ca962e9..b29367d2f7 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -79,6 +79,7 @@ /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 069ce3092c..624f0ba0d9 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -243,6 +243,14 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED bool default y +config SOC_ADC_SELF_HW_CALI_SUPPORTED + bool + default y + +config SOC_ADC_DIG_CLK_APB_SUPPORTED + bool + default y + config SOC_APB_BACKUP_DMA bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 3a3d0b4e40..20783cf3f3 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -107,6 +107,7 @@ /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (1) diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/include/soc/reg_base.h index c0ca354c00..d08aed17c6 100644 --- a/components/soc/esp32c6/include/soc/reg_base.h +++ b/components/soc/esp32c6/include/soc/reg_base.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -76,3 +76,5 @@ #define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_EXTMEM_BASE 0x600C8000 + +#define PWDET_CONF_REG 0x600A8010 diff --git a/components/soc/esp32h2/adc_periph.c b/components/soc/esp32h2/adc_periph.c index d235bdf947..524aa9af9c 100644 --- a/components/soc/esp32h2/adc_periph.c +++ b/components/soc/esp32h2/adc_periph.c @@ -10,10 +10,10 @@ const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { /* ADC1 */ { - ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM + ADC1_CHANNEL_0_GPIO_NUM, + ADC1_CHANNEL_1_GPIO_NUM, + ADC1_CHANNEL_2_GPIO_NUM, + ADC1_CHANNEL_3_GPIO_NUM, + ADC1_CHANNEL_4_GPIO_NUM, }, - /* ADC2 */ - { - ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 - } }; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 755004169c..6af4dc522b 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_ADC_SUPPORTED + bool + default y + config SOC_DEDICATED_GPIO_SUPPORTED bool default y @@ -143,10 +147,6 @@ config SOC_ADC_DIG_CTRL_SUPPORTED bool default y -config SOC_ADC_ARBITER_SUPPORTED - bool - default y - config SOC_ADC_DIG_IIR_FILTER_SUPPORTED bool default y @@ -155,6 +155,10 @@ config SOC_ADC_MONITOR_SUPPORTED bool default y +config SOC_ADC_DMA_SUPPORTED + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 @@ -179,6 +183,10 @@ config SOC_ADC_DIGI_MAX_BITWIDTH int default 12 +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + config SOC_ADC_DIGI_IIR_FILTER_NUM int default 2 @@ -187,6 +195,14 @@ config SOC_ADC_DIGI_MONITOR_NUM int default 2 +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + config SOC_ADC_SAMPLE_FREQ_THRES_HIGH int default 83333 diff --git a/components/soc/esp32h2/include/soc/adc_channel.h b/components/soc/esp32h2/include/soc/adc_channel.h index b6d038ba55..1719b65889 100644 --- a/components/soc/esp32h2/include/soc/adc_channel.h +++ b/components/soc/esp32h2/include/soc/adc_channel.h @@ -6,20 +6,17 @@ #pragma once -#define ADC1_GPIO0_CHANNEL 0 -#define ADC1_CHANNEL_0_GPIO_NUM 0 +#define ADC1_GPIO1_CHANNEL 0 +#define ADC1_CHANNEL_0_GPIO_NUM 1 -#define ADC1_GPIO1_CHANNEL 1 -#define ADC1_CHANNEL_1_GPIO_NUM 1 +#define ADC1_GPIO2_CHANNEL 1 +#define ADC1_CHANNEL_1_GPIO_NUM 2 -#define ADC1_GPIO2_CHANNEL 2 -#define ADC1_CHANNEL_2_GPIO_NUM 2 +#define ADC1_GPIO3_CHANNEL 2 +#define ADC1_CHANNEL_2_GPIO_NUM 3 -#define ADC1_GPIO3_CHANNEL 3 -#define ADC1_CHANNEL_3_GPIO_NUM 3 +#define ADC1_GPIO4_CHANNEL 3 +#define ADC1_CHANNEL_3_GPIO_NUM 4 -#define ADC1_GPIO4_CHANNEL 4 -#define ADC1_CHANNEL_4_GPIO_NUM 4 - -#define ADC2_GPIO5_CHANNEL 0 -#define ADC2_CHANNEL_0_GPIO_NUM 5 +#define ADC1_GPIO5_CHANNEL 4 +#define ADC1_CHANNEL_4_GPIO_NUM 5 diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index 330837992a..711e1fe9d7 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -367,16 +367,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of ADC digital controller */ -// TODO: temporary support, need to check while supporting -#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M} +#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST} /** * @brief ADC digital controller clock source */ -// TODO: temporary support, need to check while supporting typedef enum { ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ + ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ } soc_periph_adc_digi_clk_src_t; diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h index 3585d9e225..96d24c157b 100644 --- a/components/soc/esp32h2/include/soc/reg_base.h +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -66,3 +66,5 @@ #define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_EXTMEM_BASE 0x600C8000 + +#define PWDET_CONF_REG 0x600A8010 diff --git a/components/soc/esp32h2/include/soc/regi2c_saradc.h b/components/soc/esp32h2/include/soc/regi2c_saradc.h index b49e1ea75c..87112b2901 100644 --- a/components/soc/esp32h2/include/soc/regi2c_saradc.h +++ b/components/soc/esp32h2/include/soc/regi2c_saradc.h @@ -30,6 +30,14 @@ #define ADC_SAR2_DREF_ADDR_MSB 0x6 #define ADC_SAR2_DREF_ADDR_LSB 0x4 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 + #define I2C_SARADC_TSENS_DAC 0x6 #define I2C_SARADC_TSENS_DAC_MSB 3 #define I2C_SARADC_TSENS_DAC_LSB 3 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 1a53fcaaf0..dc0f781f29 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -25,7 +25,7 @@ #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ -// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-6214 +#define SOC_ADC_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -80,11 +80,12 @@ /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ #define SOC_ADC_DIG_CTRL_SUPPORTED 1 -#define SOC_ADC_ARBITER_SUPPORTED 1 #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 #define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +#define SOC_ADC_DMA_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (1U) -#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5) #define SOC_ADC_MAX_CHANNEL_NUM (5) #define SOC_ADC_ATTEN_NUM (4) @@ -92,8 +93,11 @@ #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) #define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) #define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */ #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 7fad95944d..5eb7a49eac 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -259,6 +259,14 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED bool default y +config SOC_ADC_SELF_HW_CALI_SUPPORTED + bool + default y + +config SOC_ADC_RTC_CLK_RC_FAST_SUPPORTED + bool + default y + config SOC_BROWNOUT_RESET_SUPPORTED bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 1dde1a6078..ceb7465574 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -117,6 +117,7 @@ /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index f11e657da4..3472a725c0 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -295,6 +295,14 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED bool default y +config SOC_ADC_SELF_HW_CALI_SUPPORTED + bool + default y + +config SOC_ADC_RTC_CLK_RC_FAST_SUPPORTED + bool + default y + config SOC_APB_BACKUP_DMA bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 983e349b68..1b53bc6262 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -109,6 +109,7 @@ /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ diff --git a/docs/docs_not_updated/esp32h2.txt b/docs/docs_not_updated/esp32h2.txt index 30a11c2aca..fb9fc7c5b7 100644 --- a/docs/docs_not_updated/esp32h2.txt +++ b/docs/docs_not_updated/esp32h2.txt @@ -44,8 +44,6 @@ api-reference/storage/mass_mfg api-reference/storage/index api-reference/storage/nvs_partition_parse api-reference/peripherals/sdspi_share -api-reference/peripherals/adc_continuous -api-reference/peripherals/adc_oneshot api-reference/peripherals/usb_host api-reference/peripherals/usb_device api-reference/peripherals/sdspi_host diff --git a/examples/peripherals/adc/continuous_read/README.md b/examples/peripherals/adc/continuous_read/README.md index 6b5d94369d..94ecfd9889 100644 --- a/examples/peripherals/adc/continuous_read/README.md +++ b/examples/peripherals/adc/continuous_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ADC DMA Example diff --git a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py index 556ddff5f5..ea513f1ff3 100644 --- a/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py +++ b/examples/peripherals/adc/continuous_read/pytest_adc_continuous.py @@ -10,6 +10,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32s3 @pytest.mark.esp32c3 @pytest.mark.esp32c6 +@pytest.mark.esp32h2 @pytest.mark.adc def test_adc_continuous(dut: Dut) -> None: res = dut.expect(r'TASK: ret is 0, ret_num is (\d+)') diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md index 8cbce51458..cc872ff214 100644 --- a/examples/peripherals/adc/oneshot_read/README.md +++ b/examples/peripherals/adc/oneshot_read/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ADC Single Read Example diff --git a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py index af2b45cfd1..9d5ad5058a 100644 --- a/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py +++ b/examples/peripherals/adc/oneshot_read/pytest_adc_oneshot.py @@ -10,6 +10,7 @@ from pytest_embedded.dut import Dut @pytest.mark.esp32s3 @pytest.mark.esp32c3 @pytest.mark.esp32c6 +@pytest.mark.esp32h2 @pytest.mark.adc def test_adc_oneshot(dut: Dut) -> None: dut.expect(r'EXAMPLE: ADC1 Channel\[(\d+)\] Raw Data: (\d+)', timeout=5)