components/bt: High level interrupt in bluetooth

components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt

components/os: high level interrupt(5)

components/os: hli_api: meta queue: fix out of bounds access, check for overflow

components/os: hli: don't spill registers, instead save them to a separate region

Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).

Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.

components/bt: using high level interrupt in lc

components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`

components/bt: optimize code structure

components/os: Modify the BT assert process to adapt to coredump and HLI

components/os: Disable exception mode after saving special registers

To store some registers first, avoid stuck due to live lock after disabling exception mode

components/os: using dport instead of AHB in BT to fix live lock

components/bt: Fix hli queue send error

components/bt: Fix CI fail

# Conflicts:
#	components/bt/CMakeLists.txt
#	components/bt/component.mk
#	components/bt/controller/bt.c
#	components/bt/controller/lib
#	components/esp_common/src/int_wdt.c
#	components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
#	components/soc/esp32/include/soc/soc.h

components/esp_ipc/src/esp_ipc_isr/esp_ipc_isr_handler.S

@@ -15,14 +15,14 @@
 
 /* High-priority interrupt - IPC_ISR handler */
 
-#define L4_INTR_STACK_SIZE  16
-#define L4_INTR_A0_OFFSET   0
-#define L4_INTR_A2_OFFSET   4
-#define L4_INTR_A3_OFFSET   8
-#define L4_INTR_A4_OFFSET   12
+#define L5_INTR_STACK_SIZE  16
+#define L5_INTR_A0_OFFSET   0
+#define L5_INTR_A2_OFFSET   4
+#define L5_INTR_A3_OFFSET   8
+#define L5_INTR_A4_OFFSET   12
     .data
-_l4_intr_stack:
-    .space      L4_INTR_STACK_SIZE
+_l5_intr_stack:
+    .space      L5_INTR_STACK_SIZE
     .section .iram1,"ax"
     .global     esp_ipc_isr_handler
     .type       esp_ipc_isr_handler,@function
@@ -32,15 +32,15 @@ esp_ipc_isr_handler:
     /* Because the interrupt cause code has protection that only
        allows one cpu to enter in the IPC_ISR section of the L4
        interrupt at one time, there's no need to have two
-       _l4_intr_stack for each cpu */
+       _l5_intr_stack for each cpu */
 
     /* Save A0, A2, A3, A4 so we can use those registers further*/
-    movi    a0, _l4_intr_stack
-    s32i    a2, a0, L4_INTR_A2_OFFSET
-    s32i    a3, a0, L4_INTR_A3_OFFSET
-    s32i    a4, a0, L4_INTR_A4_OFFSET
-    rsr     a2, EXCSAVE_4
-    s32i    a2, a0, L4_INTR_A0_OFFSET
+    movi    a0, _l5_intr_stack
+    s32i    a2, a0, L5_INTR_A2_OFFSET
+    s32i    a3, a0, L5_INTR_A3_OFFSET
+    s32i    a4, a0, L5_INTR_A4_OFFSET
+    rsr     a2, EXCSAVE_5
+    s32i    a2, a0, L5_INTR_A0_OFFSET
 
     /* disable nested iterrupts */
     /* PS.EXCM is changed from 1 to 0 . It allows using usually exception handler instead of the Double exception handler. */
@@ -85,16 +85,16 @@ esp_ipc_isr_handler:
     callx0  a0
 
     /* Done. Restore registers and return. */
-    movi    a0, _l4_intr_stack
-    l32i    a2, a0, L4_INTR_A2_OFFSET
-    l32i    a3, a0, L4_INTR_A3_OFFSET
-    l32i    a4, a0, L4_INTR_A4_OFFSET
+    movi    a0, _l5_intr_stack
+    l32i    a2, a0, L5_INTR_A2_OFFSET
+    l32i    a3, a0, L5_INTR_A3_OFFSET
+    l32i    a4, a0, L5_INTR_A4_OFFSET
 
     /* set the end flag */
     movi    a0, esp_ipc_isr_end_fl
     s32i    a0, a0, 0
 
     /* restore a0 */
-    rsr     a0, EXCSAVE_4
-    /* restores PS from EPS[4] and jumps to the address in EPC[4] */
-    rfi     4
+    rsr     a0, EXCSAVE_5
+    /* restores PS from EPS[5] and jumps to the address in EPC[5] */
+    rfi     5