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components/bt: High level interrupt in bluetooth
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
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@@ -359,7 +359,7 @@
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* 2 1 extern level
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* 3 1 extern level
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* 4 1 extern level WBB
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* 5 1 extern level BT/BLE Controller BT/BLE Controller
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* 5 1 extern level
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 7 1 software BT/BLE VHCI BT/BLE VHCI
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* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
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@@ -378,14 +378,14 @@
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* 21 2 extern level
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* 22 3 extern edge
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level
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* 24 4 extern level
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* 25 4 extern level BT/BLE Controller BT/BLE Controller
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* 26 5 extern level TG1_WDT & CACHEERR
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge IPC_ISR IPC_ISR
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* 29 3 software Reserved Reserved
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* 28 4 extern edge
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* 29 3 software BT/BLE hli BT/BLE hli
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level
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* 31 5 extern level IPC_ISR IPC_ISR
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*************************************************************************************************************
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*/
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@@ -395,11 +395,12 @@
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#define ETS_WBB_INUM 4
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#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_MEMACCESS_ERR_INUM 25
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#define ETS_T1_WDT_CACHEERR_INUM 26
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#define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM
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#define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM
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/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
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#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
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#define ETS_IPC_ISR_INUM 28
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#define ETS_IPC_ISR_INUM 31
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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