mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/fix_adc_dac_driver_ut' into 'master'
Driver(adc): fix adc driver and UT See merge request espressif/esp-idf!8482
This commit is contained in:
@@ -17,13 +17,12 @@ void adc_hal_init(void);
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void adc_hal_deinit(void);
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/**
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* Set adc sample cycle for digital controller.
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* Set adc sample cycle.
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*
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* @note Normally, please use default value.
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* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
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* Range: 2 ~ 0xFF.
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* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
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*/
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#define adc_hal_digi_set_sample_cycle(sample_cycle) adc_ll_digi_set_sample_cycle(sample_cycle)
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#define adc_hal_set_sample_cycle(sample_cycle) adc_ll_set_sample_cycle(sample_cycle)
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/**
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* Set ADC module power management.
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@@ -13,7 +13,7 @@ typedef enum {
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ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
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ADC_UNIT_2 = 2, /*!< SAR ADC 2. */
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ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
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ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
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ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */
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ADC_UNIT_MAX,
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} adc_unit_t;
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@@ -75,29 +75,58 @@ typedef enum {
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ADC_WIDTH_MAX,
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} adc_bits_width_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format option.
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*/
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typedef enum {
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ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
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Note: In single convert mode. */
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ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
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Note: In multi or alter convert mode. */
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ADC_DIGI_FORMAT_MAX,
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} adc_digi_output_format_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*
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* @note ESP32S2:
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* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
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*/
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typedef struct {
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union {
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struct {
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uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
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struct {
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uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
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uint16_t val;
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};
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} adc_digi_output_data_t;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief ADC digital controller (DMA mode) clock system setting.
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* Expression: controller_clk = (`APLL` or `APB`) * (div_num + div_b / div_a).
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* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
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*/
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typedef struct {
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bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
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uint32_t div_num; /*!<Division factor. Range: 1 ~ 255. */
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uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
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Note: When a higher frequency clock is used (the division factor is less than 9),
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the ADC reading value will be slightly offset. */
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uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
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uint32_t div_a; /*!<Division factor. Range: 1 ~ 63. */
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uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
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} adc_digi_clk_t;
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/**
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* @brief ADC digital controller (DMA mode) clock system default setting.
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*/
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#define ADC_DIGITAL_CLK_DEFAULT() { \
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.use_apll = 0, \
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.div_num = 40, \
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.div_b = 1, \
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.div_a = 1, \
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}
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/**
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* @brief ADC arbiter work mode option.
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*
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@@ -116,7 +145,7 @@ typedef enum {
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* @note ESP32S2: Only ADC2 support arbiter.
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*/
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typedef struct {
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adc_arbiter_mode_t mode; /*!<Refer to `adc_arbiter_mode_t`. Note: only support ADC2. */
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adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
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uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
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uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
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uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
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@@ -137,7 +166,11 @@ typedef struct {
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*
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* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
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* @note The conversion mode affects the sampling frequency:
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* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
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* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
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* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
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* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
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*/
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typedef enum {
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ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
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@@ -147,42 +180,6 @@ typedef enum {
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ADC_CONV_UNIT_MAX,
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} adc_digi_convert_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format option.
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*/
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typedef enum {
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ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
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Note: In single convert mode. */
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ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
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Note: In multi or alter convert mode. */
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ADC_DIGI_FORMAT_MAX,
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} adc_digi_output_format_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*
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* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
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*/
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typedef struct {
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union {
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struct {
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uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint16_t channel: 4; /*!<ADC channel index info.
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
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struct {
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uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
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uint16_t channel: 4; /*!<ADC channel index info.
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
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uint16_t val;
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};
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} adc_digi_output_data_t;
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/**
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* @brief ADC digital controller (DMA mode) conversion rules setting.
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*/
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@@ -212,26 +209,54 @@ typedef enum {
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/**
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* @brief ADC digital controller (DMA mode) configuration parameters.
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*
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* Example setting: Use ADC1 channel0 to measure voltage, the sampling rate is required to be 1KHz:
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* +---------------------+--------+--------+--------+
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* | sample rate | 1KHz | 1KHz | 1KHz |
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* +---------------------+--------+--------+--------+
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* | conv_mode | single | both | alter |
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* | adc1_pattern_len | 1 | 1 | 1 |
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* | dig_clk.use_apll | 0 | 0 | 0 |
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* | dig_clk.div_num | 99 | 99 | 99 |
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* | dig_clk.div_b | 0 | 0 | 0 |
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* | dig_clk.div_a | 0 | 0 | 0 |
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* | interval | 400 | 400 | 200 |
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* +---------------------+--------+--------+--------+
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* | `trigger_meas_freq` | 1KHz | 1KHz | 2KHz |
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* +---------------------+--------+--------+--------+
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*
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* Explain the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA output:
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* +---------------------+--------+--------+--------+
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* | conv_mode | single | both | alter |
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* +---------------------+--------+--------+--------+
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* | trigger meas times | 1 | 1 | 1 |
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* +---------------------+--------+--------+--------+
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* | conv_limit_num | +1 | +1 | +1 |
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* | dma_eof_num | +1 | +2 | +1 |
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* | dma output (byte) | +2 | +4 | +2 |
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* +---------------------+--------+--------+--------+
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*/
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typedef struct {
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bool conv_limit_en; /*!<Enable max conversion number detection for digital controller.
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If the number of ADC conversion is equal to the `limit_num`, the conversion is stopped. */
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uint32_t conv_limit_num; /*!<ADC max conversion number for digital controller. */
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uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16.
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bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
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If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
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uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
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uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
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The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
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resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
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pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
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uint32_t adc2_pattern_len; /*!<Refer to `adc1_pattern_len` */
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uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
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adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
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adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
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adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. */
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adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
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adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to ``adc1_pattern`` */
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adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
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adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
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uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
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The unit is the divided clock. Range: 40 ~ 4095. */
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adc_digi_clk_t dig_clk; /*!<Refer to `adc_digi_clk_t` */
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The unit is the divided clock. Range: 40 ~ 4095.
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Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
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Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
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adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t`` */
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uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
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If the number of measurements reaches `dma_eof_num`,
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then `dma_in_suc_eof` signal is generated. */
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If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
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Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
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} adc_digi_config_t;
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/**
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@@ -265,7 +265,7 @@ typedef struct touch_filter_config {
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uint32_t hysteresis_thr; /*!<Hysteresis threshold coefficient. hysteresis = hysteresis coefficient * touch threshold.
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If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched.
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If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released.
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Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF */
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Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 1/32; 3: OFF */
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uint32_t noise_thr; /*!<Noise threshold coefficient. noise = noise coefficient * touch threshold.
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If (raw data - baseline) > (noise), the baseline stop updating.
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If (raw data - baseline) < (noise), the baseline start updating.
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@@ -14,7 +14,7 @@
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#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
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#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
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#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
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#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
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#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (3)
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/**
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* Check if adc support digital controller (DMA) mode.
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@@ -43,7 +43,7 @@ typedef struct {
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adc_hal_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
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adc_hal_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
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adc_hal_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. ESP32 only support ADC1 single mode. */
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adc_hal_digi_output_format_t format; /*!<ADC output data format for digital controller. */
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adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
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uint32_t clk_div; /*!< ADC module clock division factor. ADC clock divided from APB clock.*/
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} adc_hal_digi_config_t;
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@@ -8,14 +8,6 @@
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extern "C" {
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#endif
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typedef enum {
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ADC_DIGI_FORMAT_12BIT, /*!< ADC to I2S data format, [15:12]-channel [11:0]-12 bits ADC data.
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Note: In single convert mode. */
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ADC_DIGI_FORMAT_11BIT, /*!< ADC to I2S data format, [15]-adc unit [14:11]-channel [10:0]-11 bits ADC data.
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Note: In multi convert mode. */
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ADC_DIGI_FORMAT_MAX,
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} adc_hal_digi_output_format_t;
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typedef enum {
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ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1*/
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ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2, not supported yet*/
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@@ -94,13 +86,12 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
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}
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/**
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* Set adc sample cycle for digital controller.
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* Set adc sample cycle.
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*
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* @note Normally, please use default value.
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* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
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* Range: 2 ~ 0xFF.
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* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
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*/
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static inline void adc_ll_digi_set_sample_cycle(uint32_t sample_cycle)
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static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
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{
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SYSCON.saradc_fsm.sample_cycle = sample_cycle;
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}
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@@ -119,9 +110,9 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
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/**
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* Set adc output data format for digital controller.
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*
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* @param format Output data format, see ``adc_hal_digi_output_format_t``.
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* @param format Output data format, see ``adc_digi_output_format_t``.
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*/
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static inline void adc_ll_digi_set_output_format(adc_hal_digi_output_format_t format)
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static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format)
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{
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SYSCON.saradc_ctrl.data_sar_sel = format;
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}
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|
@@ -94,9 +94,9 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
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/**
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* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
|
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* Enable clock and select clock source for ADC digital controller.
|
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* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
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* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
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*
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* @param clk Refer to `adc_digi_clk_t`.
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* @param clk Refer to ``adc_digi_clk_t``.
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*/
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void adc_hal_digi_clk_config(const adc_digi_clk_t *clk)
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{
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@@ -127,7 +127,7 @@ void adc_hal_digi_disable(void)
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*
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||||
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
|
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* @param adc_n ADC unit.
|
||||
* @param config Refer to `adc_digi_monitor_t`.
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||||
* @param config Refer to ``adc_digi_monitor_t``.
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||||
*/
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void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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{
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@@ -148,7 +148,7 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
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* @note Default priority: Wi-Fi > RTC > Digital;
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*
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* @param config Refer to `adc_arbiter_t`.
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* @param config Refer to ``adc_arbiter_t``.
|
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*/
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void adc_hal_arbiter_config(adc_arbiter_t *config)
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{
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|
@@ -61,6 +61,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
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||||
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||||
/**
|
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* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
|
||||
* Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
|
||||
*
|
||||
* @note The trigger interval should not be less than the sampling time of the SAR ADC.
|
||||
* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
|
||||
@@ -80,9 +81,9 @@ void adc_hal_digi_disable(void);
|
||||
/**
|
||||
* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
|
||||
* Enable clock and select clock source for ADC digital controller.
|
||||
* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
|
||||
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
|
||||
*
|
||||
* @param clk Refer to `adc_digi_clk_t`.
|
||||
* @param clk Refer to ``adc_digi_clk_t``.
|
||||
*/
|
||||
void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);
|
||||
|
||||
@@ -133,7 +134,7 @@ void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);
|
||||
*
|
||||
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
* @param config Refer to `adc_digi_monitor_t`.
|
||||
* @param config Refer to ``adc_digi_monitor_t``.
|
||||
*/
|
||||
void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config);
|
||||
|
||||
@@ -223,7 +224,7 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
|
||||
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
||||
* @note Default priority: Wi-Fi > RTC > Digital;
|
||||
*
|
||||
* @param config Refer to `adc_arbiter_t`.
|
||||
* @param config Refer to ``adc_arbiter_t``.
|
||||
*/
|
||||
void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
|
||||
|
@@ -1,11 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/adc_periph.h"
|
||||
#include "hal/adc_types.h"
|
||||
#include "soc/apb_saradc_struct.h"
|
||||
#include "soc/apb_saradc_reg.h"
|
||||
#include "soc/rtc_cntl_struct.h"
|
||||
#include <stdbool.h>
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "i2c_rtc_clk.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -51,7 +53,7 @@ typedef struct {
|
||||
|
||||
/**
|
||||
* @brief ADC controller type selection.
|
||||
*
|
||||
*
|
||||
* @note For ADC2, use the force option with care. The system power consumption detection will use ADC2.
|
||||
* If it is forced to switch to another controller, it may cause the system to obtain incorrect values.
|
||||
* @note Normally, there is no need to switch the controller manually.
|
||||
@@ -67,6 +69,49 @@ typedef enum {
|
||||
ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
|
||||
} adc_controller_t;
|
||||
|
||||
/* ADC calibration defines. */
|
||||
#define ADC_LL_I2C_ADC 0X69
|
||||
#define ADC_LL_I2C_ADC_HOSTID 0
|
||||
|
||||
#define ADC_LL_ANA_CONFIG2_REG 0x6000E048
|
||||
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
|
||||
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
|
||||
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR 0x0
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_LL_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_LL_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
/* ADC calibration defines end. */
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
@@ -89,15 +134,21 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
|
||||
}
|
||||
|
||||
/**
|
||||
* Set adc sample cycle for digital controller.
|
||||
* Set adc sample cycle.
|
||||
*
|
||||
* @note Normally, please use default value.
|
||||
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
|
||||
* Range: 2 ~ 0xFF.
|
||||
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
|
||||
*/
|
||||
static inline void adc_ll_digi_set_sample_cycle(uint32_t sample_cycle)
|
||||
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
|
||||
{
|
||||
APB_SARADC.fsm.sample_cycle = sample_cycle;
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -263,6 +314,7 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
|
||||
|
||||
/**
|
||||
* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
|
||||
* Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
|
||||
*
|
||||
* @note The trigger interval should not be less than the sampling time of the SAR ADC.
|
||||
* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
|
||||
@@ -292,11 +344,11 @@ static inline void adc_ll_digi_trigger_disable(void)
|
||||
|
||||
/**
|
||||
* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
|
||||
* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
|
||||
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
|
||||
*
|
||||
* @param div_num Division factor. Range: 1 ~ 255.
|
||||
* @param div_num Division factor. Range: 0 ~ 255.
|
||||
* @param div_b Division factor. Range: 1 ~ 63.
|
||||
* @param div_a Division factor. Range: 1 ~ 63.
|
||||
* @param div_a Division factor. Range: 0 ~ 63.
|
||||
*/
|
||||
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
|
||||
{
|
||||
@@ -1027,7 +1079,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_controller_t ct
|
||||
* @note Only ADC2 support arbiter.
|
||||
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
||||
*
|
||||
* @param mode Refer to `adc_arbiter_mode_t`.
|
||||
* @param mode Refer to ``adc_arbiter_mode_t``.
|
||||
*/
|
||||
static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode)
|
||||
{
|
||||
@@ -1092,7 +1144,7 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig,
|
||||
* In sleep mode, the arbiter is in power-down mode.
|
||||
* Need to switch the controller to RTC to shield the control of the arbiter.
|
||||
* After waking up, it needs to switch to arbiter control.
|
||||
*
|
||||
*
|
||||
* @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller.
|
||||
* @note Only support ADC2.
|
||||
*/
|
||||
@@ -1116,47 +1168,6 @@ static inline void adc_ll_disable_sleep_controller(void)
|
||||
}
|
||||
|
||||
/* ADC calibration code. */
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "i2c_rtc_clk.h"
|
||||
|
||||
#define I2C_ADC 0X69
|
||||
#define I2C_ADC_HOSTID 0
|
||||
|
||||
#define ANA_CONFIG2_REG 0x6000E048
|
||||
#define ANA_CONFIG2_M (BIT(18))
|
||||
|
||||
#define SAR1_ENCAL_GND_ADDR 0x7
|
||||
#define SAR1_ENCAL_GND_ADDR_MSB 5
|
||||
#define SAR1_ENCAL_GND_ADDR_LSB 5
|
||||
|
||||
#define SAR2_ENCAL_GND_ADDR 0x7
|
||||
#define SAR2_ENCAL_GND_ADDR_MSB 7
|
||||
#define SAR2_ENCAL_GND_ADDR_LSB 7
|
||||
|
||||
#define SAR1_INITIAL_CODE_HIGH_ADDR 0x1
|
||||
#define SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define SAR1_INITIAL_CODE_LOW_ADDR 0x0
|
||||
#define SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define SAR1_DREF_ADDR 0x2
|
||||
#define SAR1_DREF_ADDR_MSB 0x6
|
||||
#define SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define SAR2_DREF_ADDR 0x5
|
||||
#define SAR2_DREF_ADDR_MSB 0x6
|
||||
#define SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
/**
|
||||
* Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
|
||||
*
|
||||
@@ -1169,28 +1180,28 @@ static inline void adc_ll_disable_sleep_controller(void)
|
||||
*/
|
||||
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
|
||||
{
|
||||
/* Enable i2s_write_reg function. */
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
/* Enable/disable internal connect GND (for calibration). */
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_DREF_ADDR, 4);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 4);
|
||||
if (internal_gnd) {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 1);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_DREF_ADDR, 4);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 4);
|
||||
if (internal_gnd) {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 1);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 1);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1203,9 +1214,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
|
||||
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
|
||||
{
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1220,19 +1231,19 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
|
||||
{
|
||||
uint8_t msb = param >> 8;
|
||||
uint8_t lsb = param & 0xFF;
|
||||
/* Enable i2s_write_reg function. */
|
||||
/* Should be called before writing I2C registers. */
|
||||
void phy_get_romfunc_addr(void);
|
||||
phy_get_romfunc_addr();
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
} else {
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
}
|
||||
}
|
||||
/* Temp code end. */
|
||||
|
@@ -202,14 +202,14 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info);
|
||||
* Set filter mode. The input to the filter is raw data and the output is the baseline value.
|
||||
* Larger filter coefficients increase the stability of the baseline.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
|
||||
*/
|
||||
#define touch_hal_filter_set_filter_mode(mode) touch_ll_filter_set_filter_mode(mode)
|
||||
|
||||
/**
|
||||
* Get filter mode. The input to the filter is raw data and the output is the baseline value.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
|
||||
*/
|
||||
#define touch_hal_filter_get_filter_mode(mode) touch_ll_filter_get_filter_mode(mode)
|
||||
|
||||
@@ -566,7 +566,7 @@ void touch_hal_sleep_channel_get_config(touch_pad_sleep_channel_t *slp_config);
|
||||
* After the sleep channel is configured, users should query the channel reading using a specific function.
|
||||
*
|
||||
* @note ESP32S2 only support one channel to be set sleep channel.
|
||||
*
|
||||
*
|
||||
* @param pad_num touch sleep pad number.
|
||||
* @param enable Enable/disable sleep pad function.
|
||||
*/
|
||||
|
@@ -669,7 +669,7 @@ static inline void touch_ll_filter_reset_baseline(touch_pad_t touch_num)
|
||||
* Set filter mode. The input to the filter is raw data and the output is the baseline value.
|
||||
* Larger filter coefficients increase the stability of the baseline.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
|
||||
*/
|
||||
static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
|
||||
{
|
||||
@@ -679,7 +679,7 @@ static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
|
||||
/**
|
||||
* Get filter mode. The input to the filter is raw data and the output is the baseline value.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
|
||||
*/
|
||||
static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
|
||||
{
|
||||
@@ -690,7 +690,7 @@ static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
|
||||
* Set filter mode. The input to the filter is raw data and the output is the smooth data.
|
||||
* The smooth data is used to determine the touch status.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_smooth_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
|
||||
*/
|
||||
static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
|
||||
{
|
||||
@@ -700,7 +700,7 @@ static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
|
||||
/**
|
||||
* Get filter mode. The smooth data is used to determine the touch status.
|
||||
*
|
||||
* @param mode Filter mode type. Refer to `touch_smooth_mode_t`.
|
||||
* @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
|
||||
*/
|
||||
static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
|
||||
{
|
||||
|
@@ -19,7 +19,7 @@ void adc_hal_init(void)
|
||||
// Set internal FSM wait time, fixed value.
|
||||
adc_ll_digi_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
|
||||
SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
|
||||
adc_ll_digi_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
|
||||
adc_ll_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
|
||||
adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
|
||||
adc_ll_digi_output_invert(ADC_NUM_1, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_1));
|
||||
adc_ll_digi_output_invert(ADC_NUM_2, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_2));
|
||||
|
Reference in New Issue
Block a user