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spi_flash: Add ESP32-C3 support

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Based on internal commit 3ef01301fff
This commit is contained in:
Angus Gratton
2020-12-16 14:50:13 +11:00
parent c2364e133d
commit d4c9a45675
26 changed files with 493 additions and 98 deletions
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2
components/spi_flash/test/test_read_write.c
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@@ -238,7 +238,7 @@ TEST_CASE("Test spi_flash_write", "[spi_flash][esp_flash]")
* NB: At the moment these only support aligned addresses, because memcpy
* is not aware of the 32-but load requirements for these regions.
*/
#ifdef CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#define TEST_SOC_IROM_ADDR (SOC_IROM_LOW)
#define TEST_SOC_CACHE_RAM_BANK0_ADDR (SOC_IRAM_LOW)
#define TEST_SOC_CACHE_RAM_BANK1_ADDR (SOC_IRAM_LOW + 0x2000)