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Merge branch 'esp32p4/add_uart_support' into 'master'

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UART: Add uart support for ESP32P4

Closes IDF-6511 and IDF-7506

See merge request espressif/esp-idf!25388
This commit is contained in:
Gao Xu
2023-10-09 18:11:10 +08:00
parent a10121491f bc2a6bd730
commit d52040a86d
46 changed files with 1646 additions and 397 deletions
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13
components/hal/esp32/include/hal/clk_gate_ll.h
View File

@@ -266,19 +266,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
{
HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
(uart_num == 1) ? DPORT_UART1_RST :
(uart_num == 2) ? DPORT_UART2_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
(uart_num == 1) ? DPORT_UART1_CLK_EN :
(uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
}
#ifdef __cplusplus
}
#endif

78
components/hal/esp32/include/hal/uart_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,6 +15,7 @@
#include "esp_attr.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/dport_reg.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
@@ -55,6 +56,81 @@ typedef enum {
UART_INTR_CMD_CHAR_DET = (0x1<<18),
} uart_intr_t;
/**
* @brief Check if UART is enabled or disabled.
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*
* @return true: enabled; false: disabled
*/
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
(uart_num == 1) ? DPORT_UART1_RST :
(uart_num == 2) ? DPORT_UART2_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
(uart_num == 1) ? DPORT_UART1_CLK_EN :
(uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
}
/**
* @brief Enable the bus clock for uart
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
switch (uart_num) {
case 0:
reg_val = reg_val & (~DPORT_UART_CLK_EN);
reg_val = reg_val | (enable << 2);
break;
case 1:
reg_val = reg_val & (~DPORT_UART1_CLK_EN);
reg_val = reg_val | (enable << 5);
break;
case 2:
reg_val = reg_val & (~DPORT_UART2_CLK_EN);
reg_val = reg_val | (enable << 23);
break;
default:
abort();
break;
}
DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
}
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num) {
case 0:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
break;
case 1:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
break;
case 2:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
break;
default:
abort();
break;
}
}
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Set the UART source clock.
*