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refactor(rng): refactor to use hal/ll apis for c61

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Armando
2025-02-17 15:38:23 +08:00
committed by armando
parent 877057db3d
commit d598c9db7c
6 changed files with 215 additions and 114 deletions
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117
components/bootloader_support/src/bootloader_random_esp32c61.c
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@@ -1,107 +1,58 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
#include "esp_log.h"
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t SAR1_CHANNEL = 7;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 3;
static const uint32_t SAR2_ATTEN = 3;
#include "hal/regi2c_ctrl_ll.h"
#include "hal/adc_ll.h"
#include "hal/adc_types.h"
void bootloader_random_enable(void)
{
// pull SAR ADC out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
// enable SAR ADC APB clock
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
// pull APB register out of reset
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
// enable ADC_CTRL_CLK (SAR ADC function clock)
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
adc_ll_reset_register();
adc_ll_enable_bus_clock(true);
adc_ll_enable_func_clock(true);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
adc_ll_digi_controller_clk_div(0, 0, 0);
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
regi2c_ctrl_ll_i2c_reset_set();
regi2c_ctrl_ll_i2c_periph_enable();
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
adc_ll_regi2c_adc_prepare();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
adc_digi_pattern_config_t pattern_config = {};
pattern_config.unit = ADC_UNIT_1;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_7;
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
pattern_config.unit = ADC_UNIT_2;
pattern_config.atten = ADC_ATTEN_DB_12;
pattern_config.channel = ADC_CHANNEL_1;
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 2);
// create patterns and set them in pattern table
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(SARADC_SAR_PATT_TAB1_REG, pattern_table);
// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_PATT_LEN, 1);
// Same as in C3
REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_CLK_DIV, 15);
// set timer expiry (timer is ADC_CTRL_CLK)
REG_SET_FIELD(SARADC_CTRL2_REG, SARADC_TIMER_TARGET, 200);
// enable timer
REG_SET_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
adc_ll_digi_set_clk_div(15);
adc_ll_digi_set_trigger_interval(200);
adc_ll_digi_trigger_enable();
}
void bootloader_random_disable(void)
{
// disable timer
REG_CLR_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
// Write reset value of this register
REG_WRITE(SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
// Revert ADC I2C configuration and initial voltage source setting
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
adc_ll_digi_trigger_disable();
adc_ll_digi_reset_pattern_table();
adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
adc_ll_regi2c_adc_reset();
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
// Set PCR_SARADC_CONF_REG to initial state
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
adc_ll_digi_controller_clk_div(4, 0, 0);
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
}