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core system: Fix warnings in compilation when assertions are disabled

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Adds a CI config for hello world that sets this, to catch future regressions
This commit is contained in:
Angus Gratton
2021-02-12 16:01:05 +11:00
parent ac776657c9
commit d6f4d99d93
45 changed files with 114 additions and 61 deletions
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2
components/esp32/crosscore_int.c
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@@ -84,7 +84,7 @@ void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock);
reason[xPortGetCoreID()]=0;
portEXIT_CRITICAL(&reason_spinlock);
esp_err_t err;
esp_err_t err __attribute__((unused));
if (xPortGetCoreID()==0) {
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
} else {

1
components/esp32/dport_access.c
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@@ -173,6 +173,7 @@ void esp_dport_access_int_init(void)
#ifndef CONFIG_FREERTOS_UNICORE
portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
assert(res == pdTRUE);
(void)res;
#endif
}

2
components/esp32/esp_himem.c
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@@ -110,7 +110,7 @@ static inline int rangeblock_idx_valid(int rangeblock_idx)
static void set_bank(int virt_bank, int phys_bank, int ct)
{
int r;
int r __attribute__((unused));
r = cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct );
assert(r == 0);
r = cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct );