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Merge branch 'bugfix/s3_sleep_voltage' into 'master'
esp32s3: fixed dangerous power parameters in sleep modes See merge request espressif/esp-idf!18168
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@@ -112,16 +112,21 @@ set sleep_init default param
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*/
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 14
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW 15
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#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
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#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
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#define RTC_CNTL_BIASSLP_MONITOR_ON 0
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#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1
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#define RTC_CNTL_BIASSLP_SLEEP_ON 0
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#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
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#define RTC_CNTL_PD_CUR_MONITOR_ON 0
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#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1
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#define RTC_CNTL_PD_CUR_SLEEP_ON 0
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#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
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#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf
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/**
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* @brief Possible main XTAL frequency values.
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*
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@@ -585,9 +590,7 @@ typedef struct {
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uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
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uint32_t deep_slp : 1; //!< power down digital domain
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uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
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uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
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uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
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uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
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uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
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uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
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uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
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@@ -597,6 +600,7 @@ typedef struct {
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uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
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uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
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uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
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uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
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uint32_t deep_slp_reject : 1; //!< enable deep sleep reject
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uint32_t light_slp_reject : 1; //!< enable light sleep reject
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} rtc_sleep_config_t;
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