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esp_hw_support: decrease RNG read frequency on C6 and H2
* The RNG reading frequency of 200 KHz has been too high for C6 and H2 since on these chips the RNG output is combined with the RTC slow clock which is only 150KHz. Reduced the max reading frequency via esp_random() from 200KHz to 62.5KHz, which show best results in tests. Also updated the bootloader_fill_random() max frequency to the same value to be in line, even though it was just 83KHz.
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@@ -25,7 +25,8 @@
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#if !defined CONFIG_IDF_TARGET_ESP32S3
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#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
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#define RNG_CPU_WAIT_CYCLE_NUM (80 * 12) // higher frequency because we are reading bytes instead of words
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#define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
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// tested.
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#else
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#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
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#endif
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