feat(hal/usb): Make USB-DWC HAL&LL configuration independent

Previously, we included symbols from soc/usb_dwc_cfg.h and configured the HAL and LL according to it. Now we get the configuration in runtime from USB-DWC registers. Added missing definition for USB FS peripheral on ESP32-P4.
2025-09-30 19:19:21 +00:00 · 2024-10-08 12:28:46 +02:00
parent 406dfc1096
commit d837cae2b0
11 changed files with 344 additions and 257 deletions
--- a/components/soc/esp32p4/include/soc/usb_dwc_cfg.h
+++ b/components/soc/esp32p4/include/soc/usb_dwc_cfg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -11,94 +11,170 @@ extern "C" {
 #endif

 /*
+HS Instance:
 Configuration Set ID: 11
 */

 /* 3.1 Basic Config Parameters */
-#define OTG_MODE                0
-#define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        1
-#define OTG_ENABLE_LPM          0
-#define OTG_EN_DED_TX_FIFO      1
-#define OTG_EN_DESC_DMA         1
-#define OTG_MULTI_PROC_INTRPT   1
+#define OTG20_MODE                0
+#define OTG20_ARCHITECTURE        2
+#define OTG20_SINGLE_POINT        1
+#define OTG20_ENABLE_LPM          0
+#define OTG20_EN_DED_TX_FIFO      1
+#define OTG20_EN_DESC_DMA         1
+#define OTG20_MULTI_PROC_INTRPT   1

 /* 3.2 USB Physical Layer Interface Parameters */
-#define OTG_HSPHY_INTERFACE         3
-#define OTG_HSPHY_DWIDTH            2
-#define OTG_FSPHY_INTERFACE         2
-#define OTG_ENABLE_IC_USB           0
-#define OTG_ENABLE_HSIC             0
-#define OTG_I2C_INTERFACE           0
-#define OTG_ULPI_CARKIT             1
-#define OTG_ADP_SUPPORT             1
-#define OTG_BC_SUPPORT              0
-#define OTG_VENDOR_CTL_INTERFACE    1
+#define OTG20_HSPHY_INTERFACE         3
+#define OTG20_HSPHY_DWIDTH            2
+#define OTG20_FSPHY_INTERFACE         2
+#define OTG20_ENABLE_IC_USB           0
+#define OTG20_ENABLE_HSIC             0
+#define OTG20_I2C_INTERFACE           0
+#define OTG20_ULPI_CARKIT             1
+#define OTG20_ADP_SUPPORT             1
+#define OTG20_BC_SUPPORT              0
+#define OTG20_VENDOR_CTL_INTERFACE    1

 /* 3.3 Device Endpoint Configuration Parameters */
-#define OTG_NUM_EPS         15
-#define OTG_NUM_IN_EPS      8
-#define OTG_NUM_CRL_EPS     1
+#define OTG20_NUM_EPS         15
+#define OTG20_NUM_IN_EPS      8
+#define OTG20_NUM_CRL_EPS     1

 /* 3.4 Host Endpoint Configuration Parameters */
-#define OTG_NUM_HOST_CHAN   16
-#define OTG_EN_PERIO_HOST   1
+#define OTG20_NUM_HOST_CHAN   16
+#define OTG20_EN_PERIO_HOST   1

 /* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG_DFIFO_DEPTH             1024
-#define OTG_DFIFO_DYNAMIC           1
-#define OTG_RX_DFIFO_DEPTH          1024
-#define OTG_TX_HNPERIO_DFIFO_DEPTH  1024
-#define OTG_TX_HPERIO_DFIFO_DEPTH   1024
-#define OTG_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG_PERIO_TX_QUEUE_DEPTH    4
+#define OTG20_DFIFO_DEPTH             1024
+#define OTG20_DFIFO_DYNAMIC           1
+#define OTG20_RX_DFIFO_DEPTH          1024
+#define OTG20_TX_HNPERIO_DFIFO_DEPTH  1024
+#define OTG20_TX_HPERIO_DFIFO_DEPTH   1024
+#define OTG20_NPERIO_TX_QUEUE_DEPTH   4
+#define OTG20_PERIO_TX_QUEUE_DEPTH    4

 /* 3.6 Additional Configuration Options Parameters */
-#define OTG_TRANS_COUNT_WIDTH       17
-#define OTG_PACKET_COUNT_WIDTH      8
-#define OTG_RM_OPT_FEATURES         1
-#define OTG_EN_PWROPT               1
-#define OTG_SYNC_RESET_TYPE         0
-#define OTG_EN_IDDIG_FILTER         1
-#define OTG_EN_VBUSVALID_FILTER     1
-#define OTG_EN_A_VALID_FILTER       1
-#define OTG_EN_B_VALID_FILTER       1
-#define OTG_EN_SESSIONEND_FILTER    1
-#define OTG_EXCP_CNTL_XFER_FLOW     1
-#define OTG_PWR_CLAMP               0
-#define OTG_PWR_SWITCH_POLARITY     0
+#define OTG20_TRANS_COUNT_WIDTH       17
+#define OTG20_PACKET_COUNT_WIDTH      8
+#define OTG20_RM_OPT_FEATURES         1
+#define OTG20_EN_PWROPT               1
+#define OTG20_SYNC_RESET_TYPE         0
+#define OTG20_EN_IDDIG_FILTER         1
+#define OTG20_EN_VBUSVALID_FILTER     1
+#define OTG20_EN_A_VALID_FILTER       1
+#define OTG20_EN_B_VALID_FILTER       1
+#define OTG20_EN_SESSIONEND_FILTER    1
+#define OTG20_EXCP_CNTL_XFER_FLOW     1
+#define OTG20_PWR_CLAMP               0
+#define OTG20_PWR_SWITCH_POLARITY     0

 /* 3.7 Endpoint Direction Parameters */
-#define OTG_EP_DIR_1    0
-#define OTG_EP_DIR_2    0
-#define OTG_EP_DIR_3    0
-#define OTG_EP_DIR_4    0
-#define OTG_EP_DIR_5    0
-#define OTG_EP_DIR_6    0
-#define OTG_EP_DIR_7    0
-#define OTG_EP_DIR_8    0
-#define OTG_EP_DIR_9    0
-#define OTG_EP_DIR_10   0
-#define OTG_EP_DIR_11   0
-#define OTG_EP_DIR_12   0
-#define OTG_EP_DIR_13   0
-#define OTG_EP_DIR_14   0
-#define OTG_EP_DIR_15   0
+#define OTG20_EP_DIR_1    0
+#define OTG20_EP_DIR_2    0
+#define OTG20_EP_DIR_3    0
+#define OTG20_EP_DIR_4    0
+#define OTG20_EP_DIR_5    0
+#define OTG20_EP_DIR_6    0
+#define OTG20_EP_DIR_7    0
+#define OTG20_EP_DIR_8    0
+#define OTG20_EP_DIR_9    0
+#define OTG20_EP_DIR_10   0
+#define OTG20_EP_DIR_11   0
+#define OTG20_EP_DIR_12   0
+#define OTG20_EP_DIR_13   0
+#define OTG20_EP_DIR_14   0
+#define OTG20_EP_DIR_15   0

 /* 3.8 Device Periodic FIFO Depth Parameters */

 /* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG_TX_DINEP_DFIFO_DEPTH_0  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_1  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_2  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_3  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_4  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_5  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_6  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_7  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_0  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_1  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_2  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_3  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_4  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_5  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_6  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_7  512

 /* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define DWC_U2UB_EN     0
+#define OTG20_U2UB_EN     0
+
+/*
+FS Instance:
+Configuration Set ID: 1
+*/
+
+/* 3.1 Basic Config Parameters */
+#define OTG11_MODE                0
+#define OTG11_ARCHITECTURE        2
+#define OTG11_SINGLE_POINT        1
+#define OTG11_ENABLE_LPM          0
+#define OTG11_EN_DED_TX_FIFO      1
+#define OTG11_EN_DESC_DMA         1
+#define OTG11_MULTI_PROC_INTRPT   0
+
+/* 3.2 USB Physical Layer Interface Parameters */
+#define OTG11_HSPHY_INTERFACE     0
+#define OTG11_FSPHY_INTERFACE     1
+#define OTG11_ENABLE_IC_USB       0
+#define OTG11_I2C_INTERFACE       0
+#define OTG11_ADP_SUPPORT         0
+#define OTG11_BC_SUPPORT          0
+
+/* 3.3 Device Endpoint Configuration Parameters */
+#define OTG11_NUM_EPS         6
+#define OTG11_NUM_IN_EPS      5
+#define OTG11_NUM_CRL_EPS     0
+
+/* 3.4 Host Endpoint Configuration Parameters */
+#define OTG11_NUM_HOST_CHAN   8
+#define OTG11_EN_PERIO_HOST   1
+
+/* 3.5 Endpoint Channel FIFO Configuration Parameters */
+#define OTG11_DFIFO_DEPTH             256
+#define OTG11_DFIFO_DYNAMIC           1
+#define OTG11_RX_DFIFO_DEPTH          256
+#define OTG11_TX_HNPERIO_DFIFO_DEPTH  256
+#define OTG11_TX_NPERIO_DFIFO_DEPTH   256
+#define OTG11_TX_HPERIO_DFIFO_DEPTH   256
+#define OTG11_NPERIO_TX_QUEUE_DEPTH   4
+#define OTG11_PERIO_TX_QUEUE_DEPTH    8
+
+/* 3.6 Additional Configuration Options Parameters */
+#define OTG11_TRANS_COUNT_WIDTH       16
+#define OTG11_PACKET_COUNT_WIDTH      7
+#define OTG11_RM_OPT_FEATURES         1
+#define OTG11_EN_PWROPT               1
+#define OTG11_SYNC_RESET_TYPE         0
+#define OTG11_EN_IDDIG_FILTER         1
+#define OTG11_EN_VBUSVALID_FILTER     1
+#define OTG11_EN_A_VALID_FILTER       1
+#define OTG11_EN_B_VALID_FILTER       1
+#define OTG11_EN_SESSIONEND_FILTER    1
+#define OTG11_EXCP_CNTL_XFER_FLOW     1
+#define OTG11_PWR_CLAMP               0
+#define OTG11_PWR_SWITCH_POLARITY     0
+
+/* 3.7 Endpoint Direction Parameters */
+#define OTG11_EP_DIR_1    0
+#define OTG11_EP_DIR_2    0
+#define OTG11_EP_DIR_3    0
+#define OTG11_EP_DIR_4    0
+#define OTG11_EP_DIR_5    0
+#define OTG11_EP_DIR_6    0
+
+/* 3.8 Device Periodic FIFO Depth Parameters */
+
+/* 3.9 Device IN Endpoint FIFO Depth Parameters */
+#define OTG11_TX_DINEP_DFIFO_DEPTH_1  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_2  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_3  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_4  256
+
+/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
+#define OTG11_U2UB_EN     0

 #ifdef __cplusplus
 }
--- a/components/soc/esp32p4/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32p4/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -13,7 +13,10 @@ extern "C" {
 #endif

 /*
-Registers and fields were generated based on a set of configuration options.
+Registers and fields were generated based on a set of USB-DWC configuration options.
+ESP32-P4 contains 2 instances of USB-DWC with different configurations, the structure below corresponds to the HS instance.
+The FS instance contains a subset of registers from HS instance, the user (HAL) is responsible for accessing only existing fields.
+
 See ESP32-P4 "usb_dwc_cfg.h" for more details.
 */

@@ -1368,6 +1371,7 @@ _Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t st
 #endif

 extern usb_dwc_dev_t USB_DWC_HS;
+extern usb_dwc_dev_t USB_DWC_FS;

 #ifdef __cplusplus
 }