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feat(esp32c5): add esp32c5-beta3 soc header files (part1)
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laokaiyao
241
components/soc/esp32c5/include/soc/huk_struct.h
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241
components/soc/esp32c5/include/soc/huk_struct.h
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Memory data */
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/** Group: Clock gate register */
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/** Type of clk register
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* HUK Generator clock gate control register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* Write 1 to force on register clock gate.
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*/
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uint32_t clk_en:1;
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/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
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* Write 1 to force on memory clock gate.
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*/
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uint32_t mem_cg_force_on:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} huk_clk_reg_t;
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/** Group: Interrupt registers */
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/** Type of int_raw register
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* HUK Generator interrupt raw register, valid in level.
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*/
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typedef union {
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struct {
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/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the huk_prep_done_int interrupt
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*/
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uint32_t prep_done_int_raw:1;
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/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the huk_proc_done_int interrupt
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*/
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uint32_t proc_done_int_raw:1;
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/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the huk_post_done_int interrupt
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*/
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uint32_t post_done_int_raw:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} huk_int_raw_reg_t;
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/** Type of int_st register
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* HUK Generator interrupt status register.
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*/
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typedef union {
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struct {
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/** prep_done_int_st : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the huk_prep_done_int interrupt
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*/
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uint32_t prep_done_int_st:1;
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/** proc_done_int_st : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the huk_proc_done_int interrupt
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*/
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uint32_t proc_done_int_st:1;
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/** post_done_int_st : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the huk_post_done_int interrupt
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*/
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uint32_t post_done_int_st:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} huk_int_st_reg_t;
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/** Type of int_ena register
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* HUK Generator interrupt enable register.
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*/
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typedef union {
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struct {
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/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the huk_prep_done_int interrupt
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*/
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uint32_t prep_done_int_ena:1;
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/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the huk_proc_done_int interrupt
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*/
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uint32_t proc_done_int_ena:1;
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/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the huk_post_done_int interrupt
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*/
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uint32_t post_done_int_ena:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} huk_int_ena_reg_t;
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/** Type of int_clr register
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* HUK Generator interrupt clear register.
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*/
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typedef union {
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struct {
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/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the huk_prep_done_int interrupt
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*/
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uint32_t prep_done_int_clr:1;
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/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the huk_proc_done_int interrupt
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*/
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uint32_t proc_done_int_clr:1;
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/** post_done_int_clr : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the huk_post_done_int interrupt
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*/
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uint32_t post_done_int_clr:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} huk_int_clr_reg_t;
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/** Group: Configuration registers */
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/** Type of conf register
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* HUK Generator configuration register
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*/
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typedef union {
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struct {
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/** mode : R/W; bitpos: [0]; default: 0;
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* Set this field to choose the huk process. 1: process huk generate mode. 0: process
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* huk recovery mode.
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*/
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uint32_t mode:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} huk_conf_reg_t;
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/** Group: Control registers */
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/** Type of start register
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* HUK Generator control register
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*/
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typedef union {
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struct {
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/** start : WT; bitpos: [0]; default: 0;
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* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
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*/
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uint32_t start:1;
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/** continue : WT; bitpos: [1]; default: 0;
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* Write 1 to start HUK Generator at IDLE state.
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*/
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uint32_t continue:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} huk_start_reg_t;
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/** Group: State registers */
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/** Type of state register
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* HUK Generator state register
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*/
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typedef union {
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struct {
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/** state : RO; bitpos: [1:0]; default: 0;
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* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
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*/
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uint32_t state:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} huk_state_reg_t;
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/** Group: Result registers */
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/** Type of status register
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* HUK Generator HUK status register
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*/
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typedef union {
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struct {
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/** status : RO; bitpos: [1:0]; default: 0;
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* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
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* 2: HUK is generated but invalid. 3: reserved.
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*/
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uint32_t status:2;
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/** risk_level : RO; bitpos: [4:2]; default: 0;
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* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
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* are in the PUF SRAM. 7: Error Level, HUK is invalid.
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*/
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uint32_t risk_level:3;
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uint32_t reserved_5:27;
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};
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uint32_t val;
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} huk_status_reg_t;
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/** Group: Version register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36720704;
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* HUK Generator version control register.
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} huk_date_reg_t;
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typedef struct {
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uint32_t reserved_000;
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volatile huk_clk_reg_t clk;
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volatile huk_int_raw_reg_t int_raw;
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volatile huk_int_st_reg_t int_st;
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volatile huk_int_ena_reg_t int_ena;
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volatile huk_int_clr_reg_t int_clr;
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uint32_t reserved_018[2];
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volatile huk_conf_reg_t conf;
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volatile huk_start_reg_t start;
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volatile huk_state_reg_t state;
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uint32_t reserved_02c[2];
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volatile huk_status_reg_t status;
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uint32_t reserved_038[49];
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volatile huk_date_reg_t date;
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volatile uint32_t info[96];
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} huk_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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