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adc_digi: update_adc_api_for_5M_freq_limit
The ``adc_digi_config_t`` struct is modified on esp32c3: configuration of clock divider factors are not provided anymore. The SARADC sampling frequency is provided instead. In this way, we can handle the frequency limit better.
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@@ -97,7 +97,6 @@ typedef struct adc_digi_context_t {
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adc_digi_config_t digi_controller_config; //Digital Controller Configuration
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} adc_digi_context_t;
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static const char* ADC_DMA_TAG = "ADC_DMA:";
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static adc_digi_context_t *s_adc_digi_ctx = NULL;
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static uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan, adc_atten_t atten);
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@@ -344,7 +343,7 @@ esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_l
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data = xRingbufferReceiveUpTo(s_adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max);
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if (!data) {
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ESP_LOGV(ADC_DMA_TAG, "No data, increase timeout or reduce conv_num_each_intr");
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ESP_LOGV(ADC_TAG, "No data, increase timeout or reduce conv_num_each_intr");
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ret = ESP_ERR_TIMEOUT;
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*out_length = 0;
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return ret;
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@@ -428,11 +427,7 @@ int adc1_get_raw(adc1_channel_t channel)
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adc_digi_config_t dig_cfg = {
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.conv_limit_en = 0,
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.conv_limit_num = 250,
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.interval = 40,
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.dig_clk.use_apll = 0,
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.dig_clk.div_num = 15,
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.dig_clk.div_a = 0,
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.dig_clk.div_b = 1,
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.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
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};
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ADC_DIGI_LOCK_ACQUIRE();
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@@ -489,11 +484,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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adc_digi_config_t dig_cfg = {
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.conv_limit_en = 0,
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.conv_limit_num = 250,
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.interval = 40,
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.dig_clk.use_apll = 0,
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.dig_clk.div_num = 15,
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.dig_clk.div_a = 0,
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.dig_clk.div_b = 1,
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.sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
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};
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SAC_ADC2_LOCK_ACQUIRE();
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@@ -540,32 +531,34 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
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if (!s_adc_digi_ctx) {
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return ESP_ERR_INVALID_STATE;
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}
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ADC_CHECK(config->sample_freq_hz <= 83333 && config->sample_freq_hz >= 610, "ADC sampling frequency out of range", ESP_ERR_INVALID_ARG);
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s_adc_digi_ctx->digi_controller_config.conv_limit_en = config->conv_limit_en;
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s_adc_digi_ctx->digi_controller_config.conv_limit_num = config->conv_limit_num;
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s_adc_digi_ctx->digi_controller_config.adc_pattern_len = config->adc_pattern_len;
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s_adc_digi_ctx->digi_controller_config.interval = config->interval;
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s_adc_digi_ctx->digi_controller_config.dig_clk = config-> dig_clk;
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s_adc_digi_ctx->digi_controller_config.dma_eof_num = config->dma_eof_num;
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s_adc_digi_ctx->digi_controller_config.sample_freq_hz = config->sample_freq_hz;
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memcpy(s_adc_digi_ctx->digi_controller_config.adc_pattern, config->adc_pattern, config->adc_pattern_len * sizeof(adc_digi_pattern_table_t));
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//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
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s_adc_digi_ctx->adc1_atten = ADC_ATTEN_MAX;
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s_adc_digi_ctx->adc2_atten = ADC_ATTEN_MAX;
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const int atten_uninitialised = 999;
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s_adc_digi_ctx->adc1_atten = atten_uninitialised;
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s_adc_digi_ctx->adc2_atten = atten_uninitialised;
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s_adc_digi_ctx->use_adc1 = 0;
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s_adc_digi_ctx->use_adc2 = 0;
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for (int i = 0; i < config->adc_pattern_len; i++) {
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const adc_digi_pattern_table_t* pat = &config->adc_pattern[i];
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if (pat->unit == ADC_NUM_1) {
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s_adc_digi_ctx->use_adc1 = 1;
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if (s_adc_digi_ctx->adc1_atten == ADC_ATTEN_MAX) {
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if (s_adc_digi_ctx->adc1_atten == atten_uninitialised) {
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s_adc_digi_ctx->adc1_atten = pat->atten;
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} else if (s_adc_digi_ctx->adc1_atten != pat->atten) {
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return ESP_ERR_INVALID_ARG;
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}
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} else if (pat->unit == ADC_NUM_2) {
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//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
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s_adc_digi_ctx->use_adc2 = 1;
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if (s_adc_digi_ctx->adc2_atten == ADC_ATTEN_MAX) {
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if (s_adc_digi_ctx->adc2_atten == atten_uninitialised) {
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s_adc_digi_ctx->adc2_atten = pat->atten;
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} else if (s_adc_digi_ctx->adc2_atten != pat->atten) {
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return ESP_ERR_INVALID_ARG;
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