Merge branch 'feature/add_clk_tree_get_frequency_api' into 'master'

clk_tree: Stage 4 - Add a general API to get the frequency of different clocks

Closes IDF-6569

See merge request espressif/esp-idf!21830

components/hal/esp32/clk_tree_hal.c

@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/clk_tree_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/rtc.h"
+#include "hal/assert.h"
+#include "hal/log.h"
+
+static const char *CLK_HAL_TAG = "clk_hal";
+
+uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
+{
+    switch (cpu_clk_src) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        return clk_hal_xtal_get_freq_mhz();
+    case SOC_CPU_CLK_SRC_PLL:
+        return clk_ll_bbpll_get_freq_mhz();
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
+    case SOC_CPU_CLK_SRC_APLL:
+        return clk_hal_apll_get_freq_hz() / MHZ;
+    default:
+        // Unknown CPU_CLK mux input
+        HAL_ASSERT(false);
+        return 0;
+    }
+}
+
+uint32_t clk_hal_cpu_get_freq_hz(void)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    switch (source) {
+    case SOC_CPU_CLK_SRC_PLL:
+        return clk_ll_cpu_get_freq_mhz_from_pll() * MHZ;
+    case SOC_CPU_CLK_SRC_APLL: {
+        uint32_t apll_freq_hz = clk_hal_apll_get_freq_hz();
+        uint32_t divider = clk_ll_cpu_get_divider_from_apll();
+        if (divider == 0) {
+            HAL_LOGE(CLK_HAL_TAG, "Invalid cpu config");
+            return 0;
+        }
+        return apll_freq_hz / divider;
+    }
+    default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
+        return clk_hal_soc_root_get_freq_mhz(source) * MHZ / clk_ll_cpu_get_divider();
+    }
+}
+
+uint32_t clk_hal_ahb_get_freq_hz(void)
+{
+    // AHB_CLK path is highly dependent on CPU_CLK path
+    switch (clk_ll_cpu_get_src()) {
+    case SOC_CPU_CLK_SRC_PLL:
+        // AHB_CLK is a fixed value when CPU_CLK is clocked from PLL
+        return CLK_LL_AHB_MAX_FREQ_MHZ * MHZ;
+    case SOC_CPU_CLK_SRC_APLL:
+        return clk_hal_cpu_get_freq_hz() >> 1;
+    default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
+        return clk_hal_cpu_get_freq_hz();
+    }
+}
+
+uint32_t clk_hal_apb_get_freq_hz(void)
+{
+    return clk_hal_ahb_get_freq_hz();
+}
+
+uint32_t clk_hal_lp_slow_get_freq_hz(void)
+{
+    switch (clk_ll_rtc_slow_get_src()) {
+    case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
+        return SOC_CLK_RC_SLOW_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
+        return SOC_CLK_XTAL32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256:
+        return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
+    default:
+        // Unknown RTC_SLOW_CLK mux input
+        HAL_ASSERT(false);
+        return 0;
+    }
+}
+
+uint32_t clk_hal_xtal_get_freq_mhz(void)
+{
+    uint32_t freq = clk_ll_xtal_load_freq_mhz();
+    if (freq == 0) {
+        return (uint32_t)RTC_XTAL_FREQ_AUTO;
+    }
+    return freq;
+}
+
+uint32_t clk_hal_apll_get_freq_hz(void)
+{
+    uint32_t xtal_freq_mhz = clk_hal_xtal_get_freq_mhz();
+    uint32_t o_div = 0;
+    uint32_t sdm0 = 0;
+    uint32_t sdm1 = 0;
+    uint32_t sdm2 = 0;
+    clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
+    uint32_t apll_freq_hz = (uint32_t)(xtal_freq_mhz * MHZ * (4 + sdm2 + (float)sdm1/256.0 + (float)sdm0/65536.0) /
+                            (((float)o_div + 2) * 2));
+    return apll_freq_hz;
+}

components/hal/esp32/include/hal/clk_tree_ll.h

@@ -33,6 +33,8 @@ extern "C" {
 #define CLK_LL_PLL_320M_FREQ_MHZ   (320)
 #define CLK_LL_PLL_480M_FREQ_MHZ   (480)
 
+#define CLK_LL_AHB_MAX_FREQ_MHZ    CLK_LL_PLL_80M_FREQ_MHZ
+
 /* BBPLL configuration parameters at reset */
 #define CLK_LL_BBPLL_IR_CAL_DELAY_VAL          0x18
 #define CLK_LL_BBPLL_IR_CAL_EXT_CAP_VAL        0x20
@@ -150,6 +152,22 @@ static inline bool clk_ll_apll_is_fpd(void)
     return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
 }
 
+/**
+ * @brief Get APLL configuration which can be used to calculate APLL frequency
+ *
+ * @param[out] o_div  Frequency divider, 0..31
+ * @param[out] sdm0  Frequency adjustment parameter, 0..255
+ * @param[out] sdm1  Frequency adjustment parameter, 0..255
+ * @param[out] sdm2  Frequency adjustment parameter, 0..63
+ */
+static inline void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
+{
+    *o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV);
+    *sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0);
+    *sdm1 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM1);
+    *sdm2 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM2);
+}
+
 /**
  * @brief Set APLL configuration
  *
@@ -618,6 +636,26 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
     return REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1;
 }
 
+/**
+ * @brief Get CPU_CLK's APLL clock source path divider
+ *
+ * @return Divider. Returns 0 means invalid.
+ */
+static inline uint32_t clk_ll_cpu_get_divider_from_apll(void)
+{
+    // APLL path divider choice shares the same register with CPUPERIOD_SEL
+    uint32_t cpu_freq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
+    switch (cpu_freq_sel) {
+    case 0:
+        return 4;
+    case 1:
+        return 2;
+    default:
+        // Invalid CPUPERIOD_SEL value if APLL is the clock source
+        return 0;
+    }
+}
+
 /**
  * @brief Set REF_TICK divider to make REF_TICK frequency at 1MHz
  *