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Merge branch 'feature/add_clk_tree_get_frequency_api' into 'master'
clk_tree: Stage 4 - Add a general API to get the frequency of different clocks Closes IDF-6569 See merge request espressif/esp-idf!21830
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -28,6 +28,7 @@ extern "C" {
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#define CLK_LL_PLL_80M_FREQ_MHZ (80)
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#define CLK_LL_PLL_120M_FREQ_MHZ (120)
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#define CLK_LL_PLL_160M_FREQ_MHZ (160)
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#define CLK_LL_PLL_240M_FREQ_MHZ (240)
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#define CLK_LL_PLL_480M_FREQ_MHZ (480)
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@@ -717,10 +718,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
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* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
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* halves. These are the routines to work with that representation.
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*
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* @param xtal_freq_mhz XTAL frequency, in MHz
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* @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
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* otherwise there will be a conflict with the low bit, which is used to disable logs
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* in the ROM code.
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*/
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static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
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{
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// Read the status of whether disabling logging from ROM code
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uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
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// If so, need to write back this setting
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if (reg == RTC_DISABLE_ROM_LOG) {
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xtal_freq_mhz |= 1;
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}
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WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
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}
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@@ -738,7 +747,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
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uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
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if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
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xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
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return xtal_freq_reg & UINT16_MAX;
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return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
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}
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// If the format in reg is invalid
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return 0;
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