Merge branch 'feature/add_clk_tree_get_frequency_api' into 'master'

clk_tree: Stage 4 - Add a general API to get the frequency of different clocks

Closes IDF-6569

See merge request espressif/esp-idf!21830

components/hal/esp32s3/clk_tree_hal.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/clk_tree_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/rtc.h"
+#include "hal/assert.h"
+#include "hal/log.h"
+
+static const char *CLK_HAL_TAG = "clk_hal";
+
+uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
+{
+    switch (cpu_clk_src) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        return clk_hal_xtal_get_freq_mhz();
+    case SOC_CPU_CLK_SRC_PLL:
+        return clk_ll_bbpll_get_freq_mhz();
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
+    default:
+        // Unknown CPU_CLK mux input
+        HAL_ASSERT(false);
+        return 0;
+    }
+}
+
+uint32_t clk_hal_cpu_get_freq_hz(void)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    switch (source) {
+    case SOC_CPU_CLK_SRC_PLL: {
+        // PLL 320MHz, CPU 240MHz is an undetermined state
+        uint32_t pll_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        uint32_t cpu_freq_mhz = clk_ll_cpu_get_freq_mhz_from_pll();
+        if (pll_freq_mhz == CLK_LL_PLL_320M_FREQ_MHZ && cpu_freq_mhz == CLK_LL_PLL_240M_FREQ_MHZ) {
+            HAL_LOGE(CLK_HAL_TAG, "Invalid cpu config");
+            return 0;
+        }
+        return cpu_freq_mhz * MHZ;
+    }
+    default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
+        return clk_hal_soc_root_get_freq_mhz(source) * MHZ / clk_ll_cpu_get_divider();
+    }
+}
+
+uint32_t clk_hal_ahb_get_freq_hz(void)
+{
+    // AHB_CLK path is highly dependent on CPU_CLK path
+    switch (clk_ll_cpu_get_src()) {
+    case SOC_CPU_CLK_SRC_PLL:
+        // AHB_CLK is a fixed value when CPU_CLK is clocked from PLL
+        return CLK_LL_AHB_MAX_FREQ_MHZ * MHZ;
+    default: // SOC_CPU_CLK_SRC_XTAL, SOC_CPU_CLK_SRC_RC_FAST...
+        return clk_hal_cpu_get_freq_hz();
+    }
+}
+
+uint32_t clk_hal_apb_get_freq_hz(void)
+{
+    return clk_hal_ahb_get_freq_hz();
+}
+
+uint32_t clk_hal_lp_slow_get_freq_hz(void)
+{
+    switch (clk_ll_rtc_slow_get_src()) {
+    case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
+        return SOC_CLK_RC_SLOW_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
+        return SOC_CLK_XTAL32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256:
+        return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
+    default:
+        // Unknown RTC_SLOW_CLK mux input
+        HAL_ASSERT(false);
+        return 0;
+    }
+}
+
+uint32_t clk_hal_xtal_get_freq_mhz(void)
+{
+    uint32_t freq = clk_ll_xtal_load_freq_mhz();
+    if (freq == 0) {
+        HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+        return (uint32_t)RTC_XTAL_FREQ_40M;
+    }
+    return freq;
+}

components/hal/esp32s3/include/hal/clk_tree_ll.h

@@ -31,6 +31,8 @@ extern "C" {
 #define CLK_LL_PLL_320M_FREQ_MHZ   (320)
 #define CLK_LL_PLL_480M_FREQ_MHZ   (480)
 
+#define CLK_LL_AHB_MAX_FREQ_MHZ    CLK_LL_PLL_80M_FREQ_MHZ
+
 #define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
     .dac = 3, \
     .dres = 3, \
@@ -620,10 +622,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -641,7 +651,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
     if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
         xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
-        return xtal_freq_reg & UINT16_MAX;
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
     }
     // If the format in reg is invalid
     return 0;