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spi_flash: bringup for esp32c6

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Cao Sen Miao
2022-10-20 13:59:08 +08:00
parent bdefd7fb6b
commit d9f01ed43c
18 changed files with 128 additions and 118 deletions
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24
components/hal/spi_flash_hal_common.inc
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@@ -105,12 +105,28 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
// The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
#else
// On ESP32, dummy output is not supported. These dummy bits will be moved into the address
// phase (and appended as ones).
/**
* - On current chips, addr phase can support 32 bits at most.
* - Flash chip requires continuous mode bits
*
* We send continuous mode bits via the dummy output feature, so as to support
* 32-bit address.
*
* On chips without dummy output feature (ESP32, ESP32C6), we fallback to use
* addr phase to send the continuous mode bits:
* - On ESP32 (QIO), qio_dummy: 6 - 4 / 4 = 5, addr_bitlen: 24 + 4 = 28. (This
* setting exists for long time, we keep this on ESP32)
* - On ESP32C6 (QIO), qio_dummy: 6 - 8 / 4 = 4, addr_bitlen: 24 + 8 = 32
* - On future chips without dummy output feature, we follow the ESP32C6 (QIO)
* way.
* - Above two ways, the timings are same.
* - DIO is similar.
*/
if (conf_required) {
int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
dummy_cyclelen_base -= 4 / line_width;
addr_bitlen += 4; //extra 4 bits indicate the conf bits is included
dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
spi_flash_ll_set_extra_address(dev, 0);
}
#endif