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Merge branch 'feat/c5_eco2_psram_timing_tuning' into 'master'

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mspi: psram 80M timing tuning on C5 ECO2

Closes IDF-13003

See merge request espressif/esp-idf!39232
This commit is contained in:
Armando (Dou Yiwen)
2025-05-22 06:41:56 +00:00
parent 5133b89183 7d5f89fa90
commit dadcc7b9f3
25 changed files with 970 additions and 53 deletions
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2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
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@@ -55,7 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)

2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
View File

@@ -52,7 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
mspi_ll_fast_set_hs_divider(6);
mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)