Merge branch 'feat/gdma_set_burst_size_v5.3' into 'release/v5.3'

feat(gdma): return alignment constraints required by the GDMA channel (v5.3) See merge request espressif/esp-idf!31113
2025-09-30 19:19:21 +00:00 · 2024-06-11 11:59:03 +08:00
parent bee6044a24 5d844e57ed
commit dafc3b3cd5
43 changed files with 575 additions and 444 deletions
--- a/components/hal/esp32c2/include/hal/gdma_ll.h
+++ b/components/hal/esp32c2/include/hal/gdma_ll.h
@@ -48,6 +48,7 @@ extern "C" {
 #define GDMA_LL_AHB_TX_RX_SHARE_INTERRUPT  1  // TX and RX channel in the same pair will share the same interrupt source number

 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1

 ///////////////////////////////////// Common /////////////////////////////////////////

--- a/components/hal/esp32c3/include/hal/gdma_ll.h
+++ b/components/hal/esp32c3/include/hal/gdma_ll.h
@@ -48,6 +48,7 @@ extern "C" {
 #define GDMA_LL_AHB_TX_RX_SHARE_INTERRUPT  1  // TX and RX channel in the same pair will share the same interrupt source number

 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1

 ///////////////////////////////////// Common /////////////////////////////////////////

--- a/components/hal/esp32c6/include/hal/gdma_ll.h
+++ b/components/hal/esp32c6/include/hal/gdma_ll.h
@@ -51,6 +51,7 @@ extern "C" {
 #define GDMA_LL_AHB_PAIRS_PER_GROUP   3 // Number of GDMA pairs in each AHB group

 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1

 #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                                     \
    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                \
--- a/components/hal/esp32h2/include/hal/gdma_ll.h
+++ b/components/hal/esp32h2/include/hal/gdma_ll.h
@@ -51,6 +51,7 @@ extern "C" {
 #define GDMA_LL_AHB_PAIRS_PER_GROUP   3 // Number of GDMA pairs in each AHB group

 #define GDMA_LL_AHB_DESC_ALIGNMENT    4
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1

 #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                                     \
    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                \
--- a/components/hal/esp32p4/include/hal/axi_dma_ll.h
+++ b/components/hal/esp32p4/include/hal/axi_dma_ll.h
@@ -125,7 +125,7 @@ static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
 }

 /**
- * @brief Enable DMA RX channel burst reading data, disabled by default
+ * @brief Enable DMA RX channel burst reading data, always enabled
 */
 static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
@@ -139,6 +139,16 @@ static inline void axi_dma_ll_rx_enable_descriptor_burst(axi_dma_dev_t *dev, uin
    dev->in[channel].conf.in_conf0.indscr_burst_en_chn = enable;
 }

+/**
+ * @brief Set the RX channel burst size
+ */
+static inline void axi_dma_ll_rx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
+{
+    HAL_ASSERT(sz >= 8 && sz <= 128);
+    int ctz = __builtin_ctz(sz);
+    dev->in[channel].conf.in_conf0.in_burst_size_sel_chn = ctz - 3;
+}
+
 /**
 * @brief Reset DMA RX channel FSM and FIFO pointer
 */
@@ -274,11 +284,11 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 }

 /**
- * @brief Whether to enable the mean access ecc or aes domain
+ * @brief Whether to enable access to ecc or aes memory
 */
 static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->in[channel].conf.in_conf0.in_ecc_aec_en_chn = enable;
+    dev->in[channel].conf.in_conf0.in_ecc_aes_en_chn = enable;
 }

 ///////////////////////////////////// TX /////////////////////////////////////////
@@ -333,7 +343,7 @@ static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
 }

 /**
- * @brief Enable DMA TX channel burst sending data, disabled by default
+ * @brief Enable DMA TX channel burst sending data, always enabled
 */
 static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
@@ -347,6 +357,16 @@ static inline void axi_dma_ll_tx_enable_descriptor_burst(axi_dma_dev_t *dev, uin
    dev->out[channel].conf.out_conf0.outdscr_burst_en_chn = enable;
 }

+/**
+ * @brief Set the TX channel burst size
+ */
+static inline void axi_dma_ll_tx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
+{
+    HAL_ASSERT(sz >= 8 && sz <= 128);
+    int ctz = __builtin_ctz(sz);
+    dev->out[channel].conf.out_conf0.out_burst_size_sel_chn = ctz - 3;
+}
+
 /**
 * @brief Set TX channel EOF mode
 */
@@ -480,11 +500,11 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 }

 /**
- * @brief Whether to enable the mean access ecc or aes domain
+ * @brief Whether to enable access to ecc or aes memory
 */
 static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
-    dev->out[channel].conf.out_conf0.out_ecc_aec_en_chn = enable;
+    dev->out[channel].conf.out_conf0.out_ecc_aes_en_chn = enable;
 }

 ///////////////////////////////////// CRC-TX /////////////////////////////////////////
--- a/components/hal/esp32s3/include/hal/gdma_ll.h
+++ b/components/hal/esp32s3/include/hal/gdma_ll.h
@@ -62,6 +62,9 @@ extern "C" {

 #define GDMA_LL_AHB_DESC_ALIGNMENT    4

+#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1
+
 ///////////////////////////////////// Common /////////////////////////////////////////

 /**
@@ -177,20 +180,20 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
 }

 /**
- * @brief Set DMA RX channel memory block size based on the alignment requirement
- * @param align Supported value: 16/32/64
+ * @brief Set DMA RX channel memory block size based on the burst requirement
+ * @param burst_sz Supported value: 16/32/64
 */
-static inline void gdma_ll_rx_set_ext_mem_block_size(gdma_dev_t *dev, uint32_t channel, uint8_t align)
+static inline void gdma_ll_rx_set_burst_size(gdma_dev_t *dev, uint32_t channel, uint32_t burst_sz)
 {
    uint32_t block_size = 0;
-    switch (align) {
-    case 64: // 64 Bytes alignment
+    switch (burst_sz) {
+    case 64:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_64B;
        break;
-    case 32: // 32 Bytes alignment
+    case 32:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_32B;
        break;
-    case 16: // 16 Bytes alignment
+    case 16:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_16B;
        break;
    default:
@@ -461,20 +464,20 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
 }

 /**
- * @brief Set DMA TX channel memory block size based on the alignment requirement
- * @param align Supported value: 16/32/64
+ * @brief Set DMA TX channel memory block size based on the burst requirement
+ * @param burst_sz Supported value: 16/32/64
 */
-static inline void gdma_ll_tx_set_ext_mem_block_size(gdma_dev_t *dev, uint32_t channel, uint8_t align)
+static inline void gdma_ll_tx_set_burst_size(gdma_dev_t *dev, uint32_t channel, uint32_t burst_sz)
 {
    uint32_t block_size = 0;
-    switch (align) {
-    case 64: // 64 Bytes alignment
+    switch (burst_sz) {
+    case 64:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_64B;
        break;
-    case 32: // 32 Bytes alignment
+    case 32:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_32B;
        break;
-    case 16: // 16 Bytes alignment
+    case 16:
        block_size = GDMA_LL_EXT_MEM_BK_SIZE_16B;
        break;
    default:
--- a/components/hal/gdma_hal_ahb_v1.c
+++ b/components/hal/gdma_hal_ahb_v1.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -91,16 +91,16 @@ void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channe
    }
 }

-#if SOC_AHB_GDMA_SUPPORT_PSRAM
-void gdma_ahb_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align)
+#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
 {
    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
-        gdma_ll_rx_set_ext_mem_block_size(hal->dev, chan_id, align);
+        gdma_ll_rx_set_burst_size(hal->dev, chan_id, burst_sz);
    } else {
-        gdma_ll_tx_set_ext_mem_block_size(hal->dev, chan_id, align);
+        gdma_ll_tx_set_burst_size(hal->dev, chan_id, burst_sz);
    }
 }
-#endif
+#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE

 void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
 {
@@ -193,8 +193,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
    hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
 #endif
-#if SOC_AHB_GDMA_SUPPORT_PSRAM
-    hal->set_ext_mem_align = gdma_ahb_hal_set_ext_mem_align;
-#endif // SOC_AHB_GDMA_SUPPORT_PSRAM
+#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+    hal->set_burst_size = gdma_ahb_hal_set_burst_size;
+#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
    hal->priv_data = &gdma_ahb_hal_priv_data;
 }
--- a/components/hal/gdma_hal_ahb_v2.c
+++ b/components/hal/gdma_hal_ahb_v2.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -102,6 +102,17 @@ void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
    }
 }

+#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        ahb_dma_ll_rx_set_burst_size(hal->ahb_dma_dev, chan_id, burst_sz);
+    } else {
+        ahb_dma_ll_tx_set_burst_size(hal->ahb_dma_dev, chan_id, burst_sz);
+    }
+}
+#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+
 void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
 {
    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
@@ -244,5 +255,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
 #if SOC_GDMA_SUPPORT_ETM
    hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
 #endif // SOC_GDMA_SUPPORT_ETM
+#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
+    hal->set_burst_size = gdma_ahb_hal_set_burst_size;
+#endif // GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
    ahb_dma_ll_set_default_memory_range(hal->ahb_dma_dev);
 }
--- a/components/hal/gdma_hal_axi.c
+++ b/components/hal/gdma_hal_axi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -102,6 +102,15 @@ void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
    }
 }

+void gdma_axi_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_set_burst_size(hal->axi_dma_dev, chan_id, burst_sz);
+    } else {
+        axi_dma_ll_tx_set_burst_size(hal->axi_dma_dev, chan_id, burst_sz);
+    }
+}
+
 void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
 {
    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
@@ -151,6 +160,15 @@ uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
    }
 }

+void gdma_axi_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
+{
+    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
+        axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
+    } else {
+        axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
+    }
+}
+
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_axi_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
@@ -236,6 +254,8 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
    hal->read_intr_status = gdma_axi_hal_read_intr_status;
    hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
    hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
+    hal->set_burst_size = gdma_axi_hal_set_burst_size;
+    hal->enable_access_encrypt_mem = gdma_axi_hal_enable_access_encrypt_mem;
 #if SOC_GDMA_SUPPORT_CRC
    hal->clear_crc = gdma_axi_hal_clear_crc;
    hal->set_crc_poly = gdma_axi_hal_set_crc_poly;
--- a/components/hal/gdma_hal_top.c
+++ b/components/hal/gdma_hal_top.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -53,10 +53,10 @@ void gdma_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_di
    hal->enable_burst(hal, chan_id, dir, en_data_burst, en_desc_burst);
 }

-void gdma_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align)
+void gdma_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz)
 {
-    if (hal->set_ext_mem_align) {
-        hal->set_ext_mem_align(hal, chan_id, dir, align);
+    if (hal->set_burst_size) {
+        hal->set_burst_size(hal, chan_id, dir, burst_sz);
    }
 }

@@ -90,6 +90,13 @@ uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_c
    return hal->get_eof_desc_addr(hal, chan_id, dir, is_success);
 }

+void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
+{
+    if (hal->enable_access_encrypt_mem) {
+        hal->enable_access_encrypt_mem(hal, chan_id, dir, en_or_dis);
+    }
+}
+
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
--- a/components/hal/include/hal/gdma_hal.h
+++ b/components/hal/include/hal/gdma_hal.h
@@ -80,13 +80,14 @@ struct gdma_hal_context_t {
    void (*connect_peri)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id); /// Connect the channel to a peripheral
    void (*disconnect_peri)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Disconnect the channel from a peripheral
    void (*enable_burst)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst); /// Enable burst mode
-    void (*set_ext_mem_align)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align); /// Set the alignment of the external memory
    void (*set_strategy)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back); /// Set some misc strategy of the channel behaviour
+    void (*set_burst_size)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz); /// Set burst transfer size
    uint32_t (*get_intr_status_reg)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); // Get the interrupt status register address
    void (*enable_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis); /// Enable the channel interrupt
    void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt
    uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); /// Read the channel interrupt status
    uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set
+    void (*enable_access_encrypt_mem)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis); /// Enable the access to the encrypted memory
 #if SOC_GDMA_SUPPORT_CRC
    void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results
    void (*set_crc_poly)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config); /// Set the CRC polynomial
@@ -115,7 +116,7 @@ void gdma_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel

 void gdma_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);

-void gdma_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align);
+void gdma_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);

 void gdma_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back);

@@ -129,6 +130,8 @@ uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_ch

 uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);

+void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis);
+
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_build_parallel_crc_matrix(int crc_width, uint32_t crc_poly_hex, int data_width,
                                        uint32_t *lfsr_transform_matrix, uint32_t *data_transform_matrix);
--- a/components/hal/include/hal/gdma_hal_ahb.h
+++ b/components/hal/include/hal/gdma_hal_ahb.h
@@ -28,7 +28,7 @@ void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_cha

 void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);

-void gdma_ahb_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align);
+void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);

 void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back);

--- a/components/hal/include/hal/gdma_hal_axi.h
+++ b/components/hal/include/hal/gdma_hal_axi.h
@@ -28,6 +28,8 @@ void gdma_axi_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_cha

 void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);

+void gdma_axi_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);
+
 void gdma_axi_hal_set_ext_mem_align(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint8_t align);

 void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back);